From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E500A0505; Tue, 12 Apr 2022 19:42:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 868E241611; Tue, 12 Apr 2022 19:42:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E8D5B41611 for ; Tue, 12 Apr 2022 19:42:44 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23CG37dI025894 for ; Tue, 12 Apr 2022 10:42:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=0Jk+v9n5vMAxkI0d1eYJTRPUImabJAhyMeXLQDxa9es=; b=Qs62FwyN92iHnobeWs8mwHNO5c28LoIM7v6P39vjSXARPjSe2mnLccJMr2ec7PY287ZY v2YcLQzuDlYRHO43cvEVXPnx22aloNeis4Y0VZq0bTPvuHL/9XJyPwPQs1PkmK4otFLL COeKPh5Fd6o/WjXLiZwyKkJuCejaQ5yyPtdcV5JM+WXqoRfd4tMlhJbhmSsrMFqmGhcF P/20IlqiypWAQCZlt5/OgKUz9le4qQd4ee9PGJq7Q9DohB+QeVBHfY9OuNv1kr2zwElr 8wbifeFRlpL/dj88b0mck1iVxR080nY8YvcP0cQJm8klZdYaPc6GosIbWffi81xEwXKR SQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fb9nnnynj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 12 Apr 2022 10:42:44 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 12 Apr 2022 10:42:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 12 Apr 2022 10:42:42 -0700 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id F2C823F705A; Tue, 12 Apr 2022 10:42:41 -0700 (PDT) From: Srikanth Yalavarthi To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , "Srikanth Yalavarthi" Subject: [PATCH 1/1] common/cnxk: added new macros to platform layer Date: Tue, 12 Apr 2022 10:42:24 -0700 Message-ID: <20220412174224.13143-1-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: 5IJaR1p5SpwarvxnoEbKIacaf70Xos_7 X-Proofpoint-GUID: 5IJaR1p5SpwarvxnoEbKIacaf70Xos_7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-12_06,2022-04-12_02,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added new macros for pointer operations, bitwise operations, spinlocks and 32 bit read and write. Signed-off-by: Srikanth Yalavarthi --- drivers/common/cnxk/roc_bits.h | 12 ++++++++++++ drivers/common/cnxk/roc_platform.h | 28 +++++++++++++++++++--------- 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/roc_bits.h b/drivers/common/cnxk/roc_bits.h index 11216d9d63..ce3dffa08d 100644 --- a/drivers/common/cnxk/roc_bits.h +++ b/drivers/common/cnxk/roc_bits.h @@ -29,4 +29,16 @@ (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) #endif +#ifndef IS_BIT_SET +#define IS_BIT_SET(num, n) ((num) & (1 << (n))) +#endif + +#ifndef SET_BIT +#define SET_BIT(num, n) ((num) | (1 << (n))) +#endif + +#ifndef CLEAR_BIT +#define CLEAR_BIT(num, n) ((num) &= ~((1) << (n))) +#endif + #endif /* _ROC_BITS_H_ */ diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 28004b1743..3671e55c23 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -41,6 +41,7 @@ #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE #define PLT_STD_C11 RTE_STD_C11 #define PLT_PTR_ADD RTE_PTR_ADD +#define PLT_PTR_SUB RTE_PTR_SUB #define PLT_PTR_DIFF RTE_PTR_DIFF #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET @@ -70,12 +71,16 @@ #define PLT_U32_CAST(val) ((uint32_t)(val)) #define PLT_U16_CAST(val) ((uint16_t)(val)) +/* Add / Sub pointer with scalar and cast to uint64_t */ +#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x)) +#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x)) + /** Divide ceil */ -#define PLT_DIV_CEIL(x, y) \ - ({ \ - __typeof(x) __x = x; \ - __typeof(y) __y = y; \ - (__x + __y - 1) / __y; \ +#define PLT_DIV_CEIL(x, y) \ + ({ \ + __typeof(x) __x = x; \ + __typeof(y) __y = y; \ + (__x + __y - 1) / __y; \ }) #define __plt_cache_aligned __rte_cache_aligned @@ -113,10 +118,11 @@ #define plt_bitmap_scan rte_bitmap_scan #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint -#define plt_spinlock_t rte_spinlock_t -#define plt_spinlock_init rte_spinlock_init -#define plt_spinlock_lock rte_spinlock_lock -#define plt_spinlock_unlock rte_spinlock_unlock +#define plt_spinlock_t rte_spinlock_t +#define plt_spinlock_init rte_spinlock_init +#define plt_spinlock_lock rte_spinlock_lock +#define plt_spinlock_unlock rte_spinlock_unlock +#define plt_spinlock_trylock rte_spinlock_trylock #define plt_intr_callback_register rte_intr_callback_register #define plt_intr_callback_unregister rte_intr_callback_unregister @@ -165,6 +171,10 @@ #define plt_write64(val, addr) \ rte_write64_relaxed((val), (volatile void *)(addr)) +#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr)) +#define plt_write32(val, addr) \ + rte_write32_relaxed((val), (volatile void *)(addr)) + #define plt_wmb() rte_wmb() #define plt_rmb() rte_rmb() #define plt_io_wmb() rte_io_wmb() -- 2.17.1