From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3946A0093; Fri, 22 Apr 2022 06:39:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 04E44410F5; Fri, 22 Apr 2022 06:39:17 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B62A0410D5 for ; Fri, 22 Apr 2022 06:39:15 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23M1LmkR027250 for ; Thu, 21 Apr 2022 21:39:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=pKuv6bFf6uOxp72LG5KJpNT+IqxRXfSiM7ks3WhTNC8=; b=VbgWyxPt8JAld/NYsKDIJSdLON10kaXvPA8j4JLdk/C7aiYe4MEfGhkTYgzEP+HhgiPE aBw7eqESUAfS0XR9Ha3ZAIWdrv1jR4yk3UtNLwZ65q4dy41tcB4JMQUwDNwfy+klTkfT d5DBYEMn0NtnkGO+KIyydinj90xtJacKZBZLzCIY8cVJEsEFIPESzWJVt7z3AeJ4FrA/ +V+dd5fCEkNBbC+9SRM+qMkKTlibRuUX4PynaZKfe1Xo6os1QVU5DsT880mAPO1EEZV1 /5KD88/54DcjLvnMWXKQxj7rNEm/PKyIOuxPLiST98NjmpnUp0DHsXoYb0GdQmFnjqUJ BA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fhtapn1mw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 21 Apr 2022 21:39:14 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 21:39:12 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 21 Apr 2022 21:39:12 -0700 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 25D1E3F706D; Thu, 21 Apr 2022 21:39:10 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Subject: [dpdk-dev][PATCH 2/3] net/cnxk: add devargs support to parse custom SA action Date: Fri, 22 Apr 2022 10:08:56 +0530 Message-ID: <20220422043857.2154566-2-kirankumark@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422043857.2154566-1-kirankumark@marvell.com> References: <20220422043857.2154566-1-kirankumark@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: E6uIfkD3mgmuhs6G-GlIzMq5foWy9S_v X-Proofpoint-ORIG-GUID: E6uIfkD3mgmuhs6G-GlIzMq5foWy9S_v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-22_01,2022-04-21_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kiran Kumar K Adding devargs support to parse custom sa action. Devargs can be specified in the following way. -a 0002:02:00.0,custom_sa_act=1 Signed-off-by: Kiran Kumar K --- doc/guides/nics/cnxk.rst | 20 ++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev_devargs.c | 10 ++++++++-- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index 31c801fa04..e5087343ed 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -251,6 +251,26 @@ Runtime Config Options With the above configuration, application can enable inline IPsec processing for 128 outbound SAs. +- ``Enable custom SA action`` (default ``0``) + + Custom SA action can be enabled by specifying ``custom_sa_act`` ``devargs`` parameter. + + For example:: + + -a 0002:02:00.0,custom_sa_act=1 + + With the above configuration, application can enable custom SA action. This + configuration allows the potential for a MCAM entry to match many SAs, + rather than only match a single SA. + For cnxk device sa_index will be calculated based on SPI value. So, it will + be 1 to 1 mapping. By enabling this devargs and setting a MCAM rule, will + allow application to configure the sa_index as part of session create. And + later original SPI value can be updated using session update. + For example, application can set sa_index as 0 using session create as SPI value + and later can update the original SPI value (for example 0x10000001) using + session update. And create a flow rule with security action and algorithm as + RTE_PMD_CNXK_SEC_ACTION_ALG0 and sa_hi as 0x1000 and sa_lo as 0x0001. + - ``Outbound CPT LF queue size`` (default ``8200``) Size of Outbound CPT LF queue in number of descriptors can be specified by diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index 9b2beb6743..248582e1f6 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -245,6 +245,7 @@ parse_sdp_channel_mask(const char *key, const char *value, void *extra_args) #define CNXK_OUTB_NB_CRYPTO_QS "outb_nb_crypto_qs" #define CNXK_SDP_CHANNEL_MASK "sdp_channel_mask" #define CNXK_FLOW_PRE_L2_INFO "flow_pre_l2_info" +#define CNXK_CUSTOM_SA_ACT "custom_sa_act" int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) @@ -263,9 +264,10 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) struct sdp_channel sdp_chan; uint16_t rss_tag_as_xor = 0; uint16_t scalar_enable = 0; - uint8_t lock_rx_ctx = 0; + uint16_t custom_sa_act = 0; struct rte_kvargs *kvlist; uint16_t no_inl_dev = 0; + uint8_t lock_rx_ctx = 0; memset(&sdp_chan, 0, sizeof(sdp_chan)); memset(&pre_l2_info, 0, sizeof(struct flow_pre_l2_size_info)); @@ -307,6 +309,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) &parse_sdp_channel_mask, &sdp_chan); rte_kvargs_process(kvlist, CNXK_FLOW_PRE_L2_INFO, &parse_pre_l2_hdr_info, &pre_l2_info); + rte_kvargs_process(kvlist, CNXK_CUSTOM_SA_ACT, &parse_flag, + &custom_sa_act); rte_kvargs_free(kvlist); null_devargs: @@ -323,6 +327,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) dev->nix.max_sqb_count = sqb_count; dev->nix.reta_sz = reta_sz; dev->nix.lock_rx_ctx = lock_rx_ctx; + dev->nix.custom_sa_action = custom_sa_act; dev->npc.flow_prealloc_size = flow_prealloc_size; dev->npc.flow_max_priority = flow_max_priority; dev->npc.switch_header_type = switch_header_type; @@ -350,4 +355,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk, CNXK_FLOW_PRE_L2_INFO "=<0-255>/<1-255>/<0-1>" CNXK_OUTB_NB_CRYPTO_QS "=<1-64>" CNXK_NO_INL_DEV "=0" - CNXK_SDP_CHANNEL_MASK "=<1-4095>/<1-4095>"); + CNXK_SDP_CHANNEL_MASK "=<1-4095>/<1-4095>" + CNXK_CUSTOM_SA_ACT "=1"); -- 2.25.1