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From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: <jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
	"Kiran Kumar K" <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	Satha Rao <skoteshwar@marvell.com>
Cc: <dev@dpdk.org>, Akhil Goyal <gakhil@marvell.com>
Subject: [PATCH v2 21/28] net/cnxk: add capabilities for IPsec crypto algos
Date: Fri, 22 Apr 2022 16:17:02 +0530	[thread overview]
Message-ID: <20220422104709.20722-21-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20220422104709.20722-1-ndabilpuram@marvell.com>

From: Akhil Goyal <gakhil@marvell.com>

Added supported crypto algorithms for inline IPsec
offload.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 166 ++++++++++++++++++++++++++++++++++++
 1 file changed, 166 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index f32e169..6a3e636 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -62,6 +62,46 @@ static struct rte_cryptodev_capabilities cn10k_eth_sec_crypto_caps[] = {
 			}, }
 		}, }
 	},
+	{	/* AES CTR */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CTR,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 16,
+					.increment = 4
+				}
+			}, }
+		}, }
+	},
+	{	/* AES-XCBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{ .sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0,
+				},
+			}, }
+		}, }
+	},
 	{	/* SHA1 HMAC */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
@@ -82,6 +122,132 @@ static struct rte_cryptodev_capabilities cn10k_eth_sec_crypto_caps[] = {
 			}, }
 		}, }
 	},
+	{	/* SHA256 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 1,
+					.max = 1024,
+					.increment = 1
+				},
+				.digest_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 16
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA384 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 1,
+					.max = 1024,
+					.increment = 1
+				},
+				.digest_size = {
+					.min = 24,
+					.max = 48,
+					.increment = 24
+					},
+			}, }
+		}, }
+	},
+	{	/* SHA512 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+				.block_size = 128,
+				.key_size = {
+					.min = 1,
+					.max = 1024,
+					.increment = 1
+				},
+				.digest_size = {
+					.min = 32,
+					.max = 64,
+					.increment = 32
+				},
+			}, }
+		}, }
+	},
+	{	/* AES GMAC (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* NULL (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+			}, },
+		}, },
+	},
+	{	/* NULL (CIPHER) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				}
+			}, },
+		}, }
+	},
+
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-- 
2.8.4


  parent reply	other threads:[~2022-04-22 10:49 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 10:46 [PATCH v2 01/28] common/cnxk: add multi channel support for SDP send queues Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 02/28] net/cnxk: add receive channel backpressure for SDP Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 03/28] common/cnxk: add new pkind for CPT when ts is enabled Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 04/28] common/cnxk: support to configure the ts pkind in CPT Nithin Dabilpuram
2022-04-26 10:12   ` Ray Kinsella
2022-04-22 10:46 ` [PATCH v2 05/28] common/cnxk: fix SQ flush sequence Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 06/28] common/cnxk: skip probing SoC environment for CN9k Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 07/28] common/cnxk: fix issues in soft expiry disable path Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 08/28] common/cnxk: convert warning to debug print Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 09/28] common/cnxk: use aggregate level rr prio from mbox Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 10/28] net/cnxk: support loopback mode on AF VF's Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 11/28] net/cnxk: update LBK ethdev link info Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 12/28] net/cnxk: add barrier after meta batch free in scalar Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 13/28] net/cnxk: disable default inner chksum for outb inline Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 14/28] net/cnxk: fix roundup size with transport mode Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 15/28] net/cnxk: update inline device in ethdev telemetry Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 16/28] net/cnxk: change env for debug IV Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 17/28] net/cnxk: reset offload flag if reassembly is disabled Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 18/28] net/cnxk: support decrement TTL for inline IPsec Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 19/28] net/cnxk: optimize Rx fast path for security pkts Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 20/28] net/cnxk: update olflags with L3/L4 csum offload Nithin Dabilpuram
2022-04-22 10:47 ` Nithin Dabilpuram [this message]
2022-04-22 10:47 ` [PATCH v2 22/28] net/cnxk: add capabilities for IPsec options Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 23/28] net/cnxk: support security stats Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 24/28] net/cnxk: add support for flow control for outbound inline Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 25/28] net/cnxk: perform early MTU setup for eventmode Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 26/28] common/cnxk: allow lesser inline inbound sa sizes Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 27/28] net/cnxk: setup variable inline inbound SA Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 28/28] net/cnxk: fix multi-seg extraction in vwqe path Nithin Dabilpuram
2022-04-22 10:54   ` Pavan Nikhilesh Bhagavatula
2022-05-03 17:36   ` Jerin Jacob

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