From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9D53A0093; Fri, 22 Apr 2022 12:49:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4877341611; Fri, 22 Apr 2022 12:48:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EE35A42815 for ; Fri, 22 Apr 2022 12:48:29 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23M0SDFi003220 for ; Fri, 22 Apr 2022 03:48:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=xMb7f20uPoE1i3Sa3+qnglg4TONtAPLjhfi2rMEG+Kc=; b=TS0ObJZ2X0q7lBfyrjfjSdm1KFgm4kUOXP3UJbdoJ6v0lDXYCY+XFSbn1I88HnkzbNVw 2PyZN64vC/pJ4owboC0lfD52R+YhUD55jTFAdCyKEE1hzHXyQIsdkh1UyXgypyjdm0QG ZVmd/V/hJ0j/9twsftqElDQEEWdhVyp+MbF3O30SmbGnDUo0VyPpCVqBG2Xfe1oKIdcn WWUnyruOCvns/4oUt0ZARmJvUxHvhf1NFL9BJ33O5ZSCeQAzh9gnE6pdx0WLMVSY3GRT IZMCpgP24CM92d7QGuSSZ13iAocZwgYVgmlxmdwPUJvrZn9i2xHpKdD/GPoWgXHRW0be GA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fk7mk44eh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 22 Apr 2022 03:48:29 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Apr 2022 03:48:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Apr 2022 03:48:27 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id A12ED3F707F; Fri, 22 Apr 2022 03:48:25 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH v2 26/28] common/cnxk: allow lesser inline inbound sa sizes Date: Fri, 22 Apr 2022 16:17:07 +0530 Message-ID: <20220422104709.20722-26-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220422104709.20722-1-ndabilpuram@marvell.com> References: <20220422104709.20722-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: RO9R5pFUs_ljrtUbKLW0jWZhqTXFFdXa X-Proofpoint-GUID: RO9R5pFUs_ljrtUbKLW0jWZhqTXFFdXa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-22_02,2022-04-22_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Restructure SA setup to allow lesser inbound SA sizes as opposed to full Inbound SA size of 1024B with max possible Anti-Replay window. Since inbound SA size is variable, move the memset logic out of common code. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_ie_ot.c | 4 ---- drivers/common/cnxk/roc_nix_inl.c | 9 ++++++++- drivers/common/cnxk/roc_nix_inl.h | 26 +++++++++++++++++++++++--- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c index d0b7ad3..4b5823d 100644 --- a/drivers/common/cnxk/roc_ie_ot.c +++ b/drivers/common/cnxk/roc_ie_ot.c @@ -10,8 +10,6 @@ roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline) { size_t offset; - memset(sa, 0, sizeof(struct roc_ot_ipsec_inb_sa)); - if (is_inline) { sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG; sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META; @@ -33,8 +31,6 @@ roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa) { size_t offset; - memset(sa, 0, sizeof(struct roc_ot_ipsec_outb_sa)); - offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx); sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B) + 1; sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN; diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 2c013cb..887d4ad 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -14,9 +14,16 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ == 1UL << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2); PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1UL << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2); -PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024); PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2); +PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ >= + ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD); +/* Allow lesser INB SA HW sizes */ +PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ <= + PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN)); +PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ == + PLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN)); static int nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 633f090..e7bcffc 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -23,13 +23,33 @@ #define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2 8 /* OT INB HW area */ +#ifndef ROC_NIX_INL_OT_IPSEC_AR_WIN_SZ_MAX +#define ROC_NIX_INL_OT_IPSEC_AR_WIN_SZ_MAX 4096u +#endif +#define ROC_NIX_INL_OT_IPSEC_AR_WINBITS_SZ \ + (PLT_ALIGN_CEIL(ROC_NIX_INL_OT_IPSEC_AR_WIN_SZ_MAX, \ + BITS_PER_LONG_LONG) / \ + BITS_PER_LONG_LONG) +#define __ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \ + (offsetof(struct roc_ot_ipsec_inb_sa, ctx.ar_winbits) + \ + sizeof(uint64_t) * ROC_NIX_INL_OT_IPSEC_AR_WINBITS_SZ) #define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \ - PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN) + PLT_ALIGN(__ROC_NIX_INL_OT_IPSEC_INB_HW_SZ, ROC_ALIGN) /* OT INB SW reserved area */ +#ifndef ROC_NIX_INL_INB_POST_PROCESS +#define ROC_NIX_INL_INB_POST_PROCESS 1 +#endif +#if ROC_NIX_INL_INB_POST_PROCESS == 0 +#define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 0 +#else #define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128 +#endif + #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ \ - (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD) -#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10 + (1UL << (64 - __builtin_clzll(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + \ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD - 1))) +#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 \ + __builtin_ctzll(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ) /* OT OUTB HW area */ #define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ \ -- 2.8.4