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From: Ke Zhang <ke1x.zhang@intel.com>
To: xiaoyun.li@intel.com, jingjing.wu@intel.com,
	beilei.xing@intel.com, dev@dpdk.org
Cc: Ke Zhang <ke1x.zhang@intel.com>
Subject: [PATCH] net/iavf: when E810 VF interrupt disable, only receive 4 packets once, fix 4 to 1.
Date: Mon, 25 Apr 2022 08:36:28 +0000	[thread overview]
Message-ID: <20220425083628.81133-1-ke1x.zhang@intel.com> (raw)

For Rx-Queue Interrupt Setting, when vf rx interrupt
disable(INTENA=0), there are two ways to write back
descriptor to host memory:

1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:
Completed descriptors are posted to host memory according to
the internal descriptor cache policy (in other words when a
full cache line is available for write-back).

2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:
Completed descriptors also trigger the ITR. Following ITR
expiration, all leftover completed descriptors are posted to
host memory.

Changing 1) to 2) to make sure VF synchronizing with PF.

Signed-off-by: Ke Zhang <ke1x.zhang@intel.com>
---
 drivers/net/iavf/iavf_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index d6190ac24a..17c7720600 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -1833,7 +1833,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
 
 	IAVF_WRITE_REG(hw,
 		      IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
-		      0);
+		      IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
 
 	IAVF_WRITE_FLUSH(hw);
 	return 0;
-- 
2.25.1


             reply	other threads:[~2022-04-25  8:42 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-25  8:36 Ke Zhang [this message]
2022-05-19  9:29 ` [PATCH] net/iavf: fix iavf crashed on dev_stop when running in multi-process mode Ke Zhang
2022-05-19  9:30 ` [PATCH v2] net/iavf: fix Rx queue interrupt setting Ke Zhang
2022-05-19  9:56   ` Zhang, Qi Z
2022-05-20  2:39 ` [PATCH v2 0/1] " Ke Zhang
2022-05-20  2:39   ` [PATCH v2 1/1] net/iavf: " Ke Zhang
2022-05-20  2:51   ` [PATCH v2 0/1] " Zhang, Qi Z
2022-05-20  3:00 ` [PATCH v2] net/iavf: " Ke Zhang
2022-05-20  3:15   ` Zhang, Qi Z

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