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Mon, 25 Apr 2022 02:30:28 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , , Subject: [PATCH 1/2] net/mlx5: fix miss LRO validation in RxQ setup Date: Mon, 25 Apr 2022 12:30:19 +0300 Message-ID: <20220425093020.125319-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425093020.125319-1-michaelba@nvidia.com> References: <20220425093020.125319-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e35f41af-1ba2-498f-539f-08da269e3e76 X-MS-TrafficTypeDiagnostic: DM4PR12MB5134:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PkQSWkXxHrCRiTQCKkW+whII1MUo+wiHspEcI17Ssl7/1F4odTvpUX+TooONGQpXwbCw+rSbsXbCPRwKGSsu59QdxZwFWK9fUcaFTm9AkJnKPIZPO8nbo7j+P+a9FP8OeXskLifjXNjZJwZZKNeFgah4LgNHehs4JcHCUoE3rnTBfbK9wATPINoaF6q+svnvDOx7tAYWbRxPZrBRU7gSZPtELEIvN5QFcXugxQ9ysCvc4FwTKQ6me6tpwxRzTKfn+DHYyPw2ymA4Noq2qlXl7cLU6ZoJ4dlcna710ZI8g6EKKDIJiaNca1w6uBQsJIaDJtSQg6ExUisqK5jwGfr3Xvkwxq/CaMzyzseD01FFFOF4/1NqUII2M9DKh2Pu/dFxBbsK40NqOAbtpcqcKv+4m2j6B17kLTS/2IUy7HLybAOFpvnbsgZi1UgXow0Bq5xHpq6TlbIlZ2qtrWa3xRCq/mdq8bgZ/Pp6ciLwB4C33Ymot1dS5Z99Mg9KwITClcbTN6xRbTgXujVM/ibTG+132yRmaFM/JUZYnL2oFtS3lg6FZ8oUbnHa/FwlGVXPtcUBi+iFlgSnM7AM4vmDy0MFMmcW7F/CYwwRtKCXEUCVSxcQ+ln/kAOicoXJCmWyFyKmo8Pm5B7DvUZbSyLmr5ZEt/7aS4jlCbR4WJzDa8lvXsmzVPrM+H+V88wYBLZhAhVHSqg+Gddbz/4yhtu+wm2cNA== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(5660300002)(8936002)(54906003)(356005)(81166007)(40460700003)(6916009)(316002)(2906002)(7696005)(6666004)(4326008)(36860700001)(82310400005)(86362001)(6286002)(450100002)(55016003)(508600001)(36756003)(70206006)(70586007)(8676002)(336012)(1076003)(47076005)(26005)(186003)(426003)(2616005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2022 09:30:31.9883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e35f41af-1ba2-498f-539f-08da269e3e76 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5134 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mlx5_rx_queue_setup() gets from user the LRO offload. When LRO is configured, the LRO flag in rxq_data is set to 1. This patch adds validation to make sure the LRO is supported. Fixes: 17ed314 ("net/mlx5: allow LRO per Rx queue") Cc: matan@mellanox.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 981c296f29..a2d03f9f67 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -842,6 +842,14 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, dev->data->dev_conf.rxmode.offloads; bool is_extmem = false; + if ((offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) && + !priv->sh->dev_cap.lro_supported) { + DRV_LOG(ERR, + "Port %u queue %u LRO is configured but not supported.", + dev->data->port_id, idx); + rte_errno = EINVAL; + return -rte_errno; + } if (mp) { /* * The parameters should be checked on rte_eth_dev layer. -- 2.25.1