From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 92720A0510; Wed, 27 Apr 2022 09:06:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2B2A740E78; Wed, 27 Apr 2022 09:06:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2C4DD40691 for ; Wed, 27 Apr 2022 09:06:35 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23QLapYS015982; Wed, 27 Apr 2022 00:06:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5+BXyLwWJEgaasAdcyxwESQ/gNFqY7aVWtb26CN37Os=; b=jmgEPR3oZAC/gVutiwetYzpyFlmylwTihUBaRjOAygnMm2UgWwx9GKRWsfgbtE6MP4Zi kAjktN/6NqZ6IzMXRBza/8bh/bosnzAQzSvDDKdWJoapZ7Y3CJ68t2DiTp1smG6Oq/i+ FlIc/LiPQMYjAUstu0UPIuzd1r+IgLuvvdElLd8ZNr35VCUYsCshTM8089gPV5mOBK+b 0yVwM912vHBbGYCAws8fN2AT6f8y6ePT3gZpRMnFGPenu1s0J+0MIkLL/MzjC5yNQXw5 LR6M+PW0WZKxk3WWUY+GkhI4XFhy49wQQy6Q0pIkbcT33IpU8beVVX/S7R43GPwmfHf2 GQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fprt4hnuj-20 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Apr 2022 00:06:31 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 00:06:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Apr 2022 00:06:29 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.193.69.50]) by maili.marvell.com (Postfix) with ESMTP id 4B2F05B6947; Wed, 27 Apr 2022 00:06:26 -0700 (PDT) From: Pavan Nikhilesh To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , "Pavan Nikhilesh" , Shijith Thotton CC: Subject: [PATCH] event/cnxk: add SLMTST support to Tx adapter Date: Wed, 27 Apr 2022 12:36:24 +0530 Message-ID: <20220427070624.9258-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: SpsykiSCfN6ZCT6VXj-g7iOLsQKhQRTV X-Proofpoint-GUID: SpsykiSCfN6ZCT6VXj-g7iOLsQKhQRTV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-27_02,2022-04-26_02,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Scheduled LMTST uses in-core LSW (LMTST scheduling widget) to coordinate with SSO and send a LMTST to the destination coprocessor without the need for the core to be the head of the scheduling context it is currently holding. Use SLMTST to send mbuf to NIX-TX for transmit. SLMTST only supports transmitting a single WQE. Signed-off-by: Pavan Nikhilesh --- Depends-on: Series-22634 drivers/common/cnxk/hw/ssow.h | 7 +++++++ drivers/common/cnxk/roc_dev_priv.h | 6 ++++++ drivers/common/cnxk/roc_io.h | 8 ++++++++ drivers/common/cnxk/roc_io_generic.h | 7 +++++++ drivers/common/cnxk/roc_nix.c | 19 +++++++++++++++++++ drivers/common/cnxk/roc_nix.h | 4 ++++ drivers/common/cnxk/roc_sso.c | 23 +++++++++++++++++++++++ drivers/common/cnxk/roc_sso.h | 2 ++ drivers/common/cnxk/version.map | 2 ++ drivers/event/cnxk/cn10k_eventdev.c | 11 +++++++++++ drivers/event/cnxk/cn10k_worker.h | 19 +++++++++++++------ drivers/event/cnxk/cnxk_eventdev.h | 2 +- 12 files changed, 103 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/hw/ssow.h b/drivers/common/cnxk/hw/ssow.h index 618ab7973b..b40238bc6c 100644 --- a/drivers/common/cnxk/hw/ssow.h +++ b/drivers/common/cnxk/hw/ssow.h @@ -62,6 +62,13 @@ #define SSOW_GW_RESULT_GW_NO_WORK (0x1ull) /* [CN10K, .) */ #define SSOW_GW_RESULT_GW_ERROR (0x2ull) /* [CN10K, .) */ +#define SSOW_LSW_MODE_NO_LSW (0x0) +#define SSOW_LSW_MODE_WAIT (0x1) +#define SSOW_LSW_MODE_IMMED (0x2) + +#define SSOW_LSW_WQE_RELEASE_WAIT_ACK (0x0) +#define SSOW_LSW_WQE_RELEASE_IMMED (0x1) + #define SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT 63 #define SSOW_LF_GWS_TAG_PEND_SWITCH_BIT 62 #define SSOW_LF_GWS_TAG_PEND_DESCHED_BIT 58 diff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h index 302dc0feb0..e301487f4c 100644 --- a/drivers/common/cnxk/roc_dev_priv.h +++ b/drivers/common/cnxk/roc_dev_priv.h @@ -54,6 +54,12 @@ dev_get_pf(uint16_t pf_func) return (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; } +static inline int +dev_get_func(uint16_t pf_func) +{ + return (pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; +} + static inline int dev_pf_func(int pf, int vf) { diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h index 62e98d9d00..6a76e3fa71 100644 --- a/drivers/common/cnxk/roc_io.h +++ b/drivers/common/cnxk/roc_io.h @@ -154,6 +154,14 @@ roc_lmt_submit_steorl(uint64_t data, plt_iova_t io_address) [rs] "r"(io_address)); } +static __plt_always_inline void +roc_lmt_submit_stsmaxl(uint64_t data, plt_iova_t io_address) +{ + asm volatile(".cpu generic+lse\n" + "stsmaxl %x[d], [%[rs]]" ::[d] "r"(data), + [rs] "r"(io_address)); +} + static __plt_always_inline void roc_lmt_mov(void *out, const void *in, const uint32_t lmtext) { diff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h index 42764455cc..097ed8af09 100644 --- a/drivers/common/cnxk/roc_io_generic.h +++ b/drivers/common/cnxk/roc_io_generic.h @@ -98,6 +98,13 @@ roc_lmt_submit_steorl(uint64_t data, plt_iova_t io_address) PLT_SET_USED(io_address); } +static __plt_always_inline void +roc_lmt_submit_stsmaxl(uint64_t data, plt_iova_t io_address) +{ + PLT_SET_USED(data); + PLT_SET_USED(io_address); +} + static __plt_always_inline void roc_lmt_mov(void *out, const void *in, const uint32_t lmtext) { diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 151d8c3426..16d707b5ff 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -139,6 +139,25 @@ roc_nix_max_pkt_len(struct roc_nix *roc_nix) return NIX_RPM_MAX_HW_FRS; } +int +roc_nix_sched_lmt_enable(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = (&nix->dev)->mbox; + struct lmtst_tbl_setup_req *req; + + req = mbox_alloc_msg_lmtst_tbl_setup(mbox); + if (req == NULL) + return -ENOSPC; + req->pcifunc = 0; + req->ssow_pf_func = dev_get_pf(idev_sso_pffunc_get()) << 8; + req->ssow_pf_func |= + (uint64_t)(dev_get_func(idev_sso_pffunc_get()) & 0xFF); + req->sched_ena = 1; + + return mbox_process(mbox); +} + int roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq, uint64_t rx_cfg) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index dbb816d961..b985fb5df4 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -904,4 +904,8 @@ int __roc_api roc_nix_mcast_mcam_entry_write(struct roc_nix *roc_nix, uint64_t action); int __roc_api roc_nix_mcast_mcam_entry_ena_dis(struct roc_nix *roc_nix, uint32_t index, bool enable); + +/* SSO */ +int __roc_api roc_nix_sched_lmt_enable(struct roc_nix *roc_nix); + #endif /* _ROC_NIX_H_ */ diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index f8a0a96533..1b76b439d0 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -344,6 +344,29 @@ roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp, return 0; } +int +roc_sso_hws_config_lsw(struct roc_sso *roc_sso, uint8_t lsw_mode, + uint8_t wqe_release_mode) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct ssow_config_lsw *req; + + if (lsw_mode > SSOW_LSW_MODE_IMMED || + wqe_release_mode > SSOW_LSW_WQE_RELEASE_IMMED) + return -EINVAL; + + req = mbox_alloc_msg_ssow_config_lsw(dev->mbox); + if (req == NULL) + return -ENOSPC; + + req->lsw_mode = lsw_mode; + req->wqe_release = wqe_release_mode; + if (mbox_process(dev->mbox) < 0) + return -EIO; + + return 0; +} + int roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp) diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index ab7cee1c60..4548f78602 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -102,6 +102,8 @@ int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp); int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp); +int __roc_api roc_sso_hws_config_lsw(struct roc_sso *roc_sso, uint8_t lsw_mode, + uint8_t wqe_release_mode); int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp); uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 2a122e544d..9c3fe1d31a 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -230,6 +230,7 @@ INTERNAL { roc_nix_rx_drop_re_set; roc_nix_rx_queue_intr_disable; roc_nix_rx_queue_intr_enable; + roc_nix_sched_lmt_enable; roc_nix_sq_dump; roc_nix_sq_fini; roc_nix_sq_head_tail_get; @@ -348,6 +349,7 @@ INTERNAL { roc_sso_hwgrp_set_priority; roc_sso_hwgrp_stats_get; roc_sso_hws_base_get; + roc_sso_hws_config_lsw; roc_sso_hws_link; roc_sso_hws_stats_get; roc_sso_hws_unlink; diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 9b4d2895ec..31dca54ccc 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -57,6 +57,7 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id) ws->swtag_req = 0; ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev); ws->lmt_base = dev->sso.lmt_base; + ws->gw_rdata = (SSO_TT_EMPTY << 32) | BIT_ULL(35); return ws; } @@ -567,12 +568,18 @@ cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, static int cn10k_sso_start(struct rte_eventdev *event_dev) { + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); int rc; rc = cn10k_sso_updt_tx_adptr_data(event_dev); if (rc < 0) return rc; + rc = roc_sso_hws_config_lsw(&dev->sso, SSO_LSW_MODE_WAITW, + SSOW_LSW_WQE_RELEASE_IMMED); + if (rc < 0) + return rc; + rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset, cn10k_sso_hws_flush_events); if (rc < 0) @@ -756,6 +763,10 @@ cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev, uint64_t tx_offloads; int rc; + rc = roc_nix_sched_lmt_enable(&cnxk_eth_dev->nix); + if (rc < 0) + return -EINVAL; + RTE_SET_USED(id); rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id); if (rc < 0) diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index c96048f47d..7f36b0020e 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -580,11 +580,18 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd, else pa = txq->io_addr | ((segdw - 1) << 4); - if (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type) - ws->gw_rdata = roc_sso_hws_head_wait(ws->base); + if (flags & NIX_TX_VWQE_F || + CNXK_TT_FROM_TAG(ws->gw_rdata) == SSO_TT_EMPTY) { + if (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type) + ws->gw_rdata = roc_sso_hws_head_wait(ws->base); - cn10k_sso_txq_fc_wait(txq); - roc_lmt_submit_steorl(lmt_id, pa); + cn10k_sso_txq_fc_wait(txq); + roc_lmt_submit_steorl(lmt_id, pa); + } else { + cn10k_sso_txq_fc_wait(txq); + roc_lmt_submit_stsmaxl( + (uint64_t)lmt_id | (uint64_t)ws->hws_id << 16, pa); + } } static __rte_always_inline void @@ -616,7 +623,7 @@ cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs, for (j = 0; j < 4; j++) cn10k_sso_tx_one(ws, mbufs[i + j], cmd, lmt_id, lmt_addr, sched_type, txq_data, - flags); + flags | NIX_TX_VWQE_F); } else { txq = (struct cn10k_eth_txq *)(txq_data[(txq_data[port[0]] >> 48) + @@ -632,7 +639,7 @@ cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs, for (i = 0; i < scalar; i++) { cn10k_sso_tx_one(ws, mbufs[i], cmd, lmt_id, lmt_addr, - sched_type, txq_data, flags); + sched_type, txq_data, flags | NIX_TX_VWQE_F); } } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 5564746e6d..1cf6517e73 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -129,13 +129,13 @@ struct cn10k_sso_hws { void *lookup_mem; uint32_t gw_wdata; uint8_t swtag_req; - uint8_t hws_id; /* Add Work Fastpath data */ uint64_t xaq_lmt __rte_cache_aligned; uint64_t *fc_mem; uintptr_t grp_base; /* Tx Fastpath data */ uintptr_t lmt_base __rte_cache_aligned; + uint8_t hws_id; uint64_t lso_tun_fmt; uint8_t tx_adptr_data[]; } __rte_cache_aligned; -- 2.25.1