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From: Stephen Hemminger <stephen@networkplumber.org>
To: "Stanisław Kardach" <kda@semihalf.com>
Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,
	dev <dev@dpdk.org>, Frank Zhao <Frank.Zhao@starfivetech.com>,
	Sam Grove <sam.grove@sifive.com>, Marcin Wojtas <mw@semihalf.com>,
	upstream@semihalf.com
Subject: Re: [PATCH 09/11] test/ring: disable problematic tests for RISC-V
Date: Thu, 5 May 2022 11:06:33 -0700	[thread overview]
Message-ID: <20220505110633.014ca59a@hermes.local> (raw)
In-Reply-To: <CALVGJWKiqaSEBD9zm-C-7z3QeK9Q=GSkgbhfrVfe-k3jWGDx-g@mail.gmail.com>

On Thu, 5 May 2022 19:43:43 +0200
Stanisław Kardach <kda@semihalf.com> wrote:

> On Thu, May 5, 2022 at 7:35 PM Stephen Hemminger <stephen@networkplumber.org>
> wrote:
> 
> > On Thu,  5 May 2022 19:30:01 +0200
> > Stanislaw Kardach <kda@semihalf.com> wrote:
> >  
> > > When compiling for RISC-V in debug mode the large amount of inlining in
> > > test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c)
> > > leads to large loop bodies. This causes 'goto' and 'for' loop
> > > PC-relative jumps generated by the compiler to go beyond the architecture
> > > limitation of +/-1MB offset (the 'j <offset>' instruction). This
> > > instruction should not be generated by the compiler since C language does
> > > not limit the maximum distance for 'goto' or 'for' loop jumps.
> > >
> > > This only happens in the unit test for ring which tries to perform long
> > > loops with ring enqueue/dequeue and it seems to be caused by excessive
> > > __rte_always_inline usage. ring perf test compiles just fine under
> > > debug.
> > >
> > > To work around this, disable the offending tests in debug mode.
> > >
> > > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > > Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> > > Sponsored-by: Sam Grove <sam.grove@sifive.com>
> > > ---  
> >
> > It seems to me that fixing the excessive inlining in the ring code
> > could benefit all architectures, rather than neutering the tests
> > on RISCV.
> >  
>  True. Since this only happened in the tests that I've mentioned, my other
> approach was to introduce a "slow" wrapper over test_ring_dequeue|enqueue()
> which did not force inlining via __rte_always_inline and use it in
> functional test functions. However after talking with Thomas Monjalon we've
> decided to guard the debug build of RISC-V only.
> Another thing is that this is a clear bug in the compiler, the relaxation
> of the jump should not be done since RISC-V has long jump construct for
> arbitrary jumps (auipc+jalr).

There is no good reason the __rte_always_inline should be in the ring code.
The purpose of always inline should be only for code that would break if
not inlined.

  reply	other threads:[~2022-05-05 18:06 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 17:29 [PATCH 00/11] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 01/11] lpm: add a scalar version of lookupx4 function Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Stanislaw Kardach
2022-05-05 17:39   ` Stephen Hemminger
2022-05-05 17:49     ` Stanisław Kardach
2022-05-05 18:09       ` Stephen Hemminger
2022-05-05 17:29 ` [PATCH 03/11] eal: add initial support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 07/11] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 09/11] test/ring: disable problematic tests for RISC-V Stanislaw Kardach
2022-05-05 17:35   ` Stephen Hemminger
2022-05-05 17:43     ` Stanisław Kardach
2022-05-05 18:06       ` Stephen Hemminger [this message]
2022-05-10 23:28   ` Honnappa Nagarahalli
2022-05-11 10:07     ` Stanisław Kardach
2022-05-05 17:30 ` [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 11/11] test/hash: report non HTM numbers for single r/w Stanislaw Kardach
2022-05-06  9:13 ` [PATCH 00/11] Introduce support for RISC-V architecture David Marchand
2022-05-09 12:24   ` Stanisław Kardach
2022-05-09 12:30     ` Thomas Monjalon
2022-05-11  8:09       ` Morten Brørup
2022-05-11 10:28         ` Stanisław Kardach
2022-05-11 11:06           ` Thomas Monjalon
2022-05-09 14:30     ` David Marchand
2022-05-10 11:21       ` Stanisław Kardach
2022-05-10 12:31         ` Thomas Monjalon
2022-05-10 14:00           ` Stanisław Kardach
2022-05-10 14:23             ` Thomas Monjalon
2022-05-10 15:07 ` [PATCH v2 0/8] " Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 1/8] eal: add initial " Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:35     ` Stanisław Kardach
2022-05-10 15:07   ` [PATCH v2 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-10 15:48   ` [PATCH v3 0/8] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 1/8] eal: add initial " Stanislaw Kardach
2022-05-13  6:50       ` Heinrich Schuchardt
2022-05-13  8:42         ` Stanisław Kardach
2022-05-13 10:51           ` Heinrich Schuchardt
2022-05-13 11:47             ` Stanisław Kardach
2022-05-13 15:37         ` Stephen Hemminger
2022-05-16  8:00           ` Stanisław Kardach
2022-05-10 15:48     ` [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-12 15:47       ` Aaron Conole
2022-05-12 16:07         ` Stanisław Kardach
2022-05-13 14:33           ` Aaron Conole
2022-05-12  8:04 ` [PATCH 00/11] Introduce support for RISC-V architecture Heinrich Schuchardt
2022-05-12  8:35   ` Stanisław Kardach
2022-05-12  9:46     ` Heinrich Schuchardt
2022-05-12 13:56       ` Stanisław Kardach
2022-05-12 21:06         ` Heinrich Schuchardt

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