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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5227.15 via Frontend Transport; Fri, 6 May 2022 03:57:09 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Fri, 6 May 2022 03:57:08 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 20:57:06 -0700 From: Spike Du To: , , , CC: , Subject: [RFC v1 3/7] ethdev: introduce Rx queue based limit watermark Date: Fri, 6 May 2022 06:56:41 +0300 Message-ID: <20220506035645.4101714-4-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220506035645.4101714-1-spiked@nvidia.com> References: <20220401032232.1267376-2-spiked@nvidia.com> <20220506035645.4101714-1-spiked@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 35e38f4a-7ab1-4234-6575-08da2f147e53 X-MS-TrafficTypeDiagnostic: SN6PR12MB2686:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2022 03:57:09.0498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35e38f4a-7ab1-4234-6575-08da2f147e53 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2686 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LWM(limit watermark) is a per Rx queue attribute that notifies dpdk application event of RTE_ETH_EVENT_RXQ_LIMIT_REACHED when the Rx queue's usable descriptor is under the watermark. To simplify its configuration, LWM is a percentage of Rx queue descriptor size with valid value of [0,99]. Setting LWM to 0 means disable it. Add LWM's configuration handle in eth_dev_ops. Signed-off-by: Spike Du --- lib/ethdev/ethdev_driver.h | 7 +++++++ lib/ethdev/rte_ethdev.c | 28 ++++++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 30 +++++++++++++++++++++++++++++- lib/ethdev/version.map | 3 +++ 4 files changed, 67 insertions(+), 1 deletion(-) diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h index 69d9dc2..1e9cdbf 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -470,6 +470,10 @@ typedef int (*eth_rx_queue_setup_t)(struct rte_eth_dev *dev, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool); +typedef int (*eth_rx_queue_set_lwm_t)(struct rte_eth_dev *dev, + uint16_t rx_queue_id, + uint8_t lwm); + /** @internal Setup a transmit queue of an Ethernet device. */ typedef int (*eth_tx_queue_setup_t)(struct rte_eth_dev *dev, uint16_t tx_queue_id, @@ -1283,6 +1287,9 @@ struct eth_dev_ops { /** Dump private info from device */ eth_dev_priv_dump_t eth_dev_priv_dump; + + /** Set Rx queue limit watermark */ + eth_rx_queue_set_lwm_t rx_queue_set_lwm; }; /** diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 29a3d80..1e4fc6a 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -4414,6 +4414,34 @@ int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx, queue_idx, tx_rate)); } +int rte_eth_rx_queue_set_lwm(uint16_t port_id, uint16_t queue_idx, + uint8_t lwm) +{ + struct rte_eth_dev *dev; + struct rte_eth_dev_info dev_info; + int ret; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + dev = &rte_eth_devices[port_id]; + + ret = rte_eth_dev_info_get(port_id, &dev_info); + if (ret != 0) + return ret; + + if (queue_idx > dev_info.max_rx_queues) { + RTE_ETHDEV_LOG(ERR, + "Set queue rate limit:port %u: invalid queue ID=%u\n", + port_id, queue_idx); + return -EINVAL; + } + + if (lwm > 99) + return -EINVAL; + RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_set_lwm, -ENOTSUP); + return eth_err(port_id, (*dev->dev_ops->rx_queue_set_lwm)(dev, + queue_idx, lwm)); +} + RTE_INIT(eth_dev_init_fp_ops) { uint32_t i; diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 04cff8e..f29e53b 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -1249,8 +1249,12 @@ struct rte_eth_rxconf { */ union rte_eth_rxseg *rx_seg; - uint64_t reserved_64s[2]; /**< Reserved for future fields */ + uint64_t reserved_64s; + uint32_t reserved_32s; + uint32_t lwm:8; + uint32_t reserved_bits:24; void *reserved_ptrs[2]; /**< Reserved for future fields */ + }; /** @@ -3668,6 +3672,29 @@ int rte_eth_dev_set_vlan_ether_type(uint16_t port_id, */ int rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on); +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Set Rx queue based limit watermark. + * + * @param port_id + * The port identifier of the Ethernet device. + * @param queue_idx + * The index of the receive queue + * @param lwm + * The limit watermark percentage of Rx queue descriptor size. + * The valid range is [0,99]. + * Setting 0 means disable limit watermark. + * + * @return + * - (0) if successful. + * - negative if failed. + */ +__rte_experimental +int rte_eth_rx_queue_set_lwm(uint16_t port_id, uint16_t queue_idx, + uint8_t lwm); + typedef void (*buffer_tx_error_fn)(struct rte_mbuf **unsent, uint16_t count, void *userdata); @@ -3873,6 +3900,7 @@ enum rte_eth_event_type { RTE_ETH_EVENT_DESTROY, /**< port is released */ RTE_ETH_EVENT_IPSEC, /**< IPsec offload related event */ RTE_ETH_EVENT_FLOW_AGED,/**< New aged-out flows is detected */ + RTE_ETH_EVENT_RXQ_LIMIT_REACHED,/**< RX queue limit reached */ RTE_ETH_EVENT_MAX /**< max value of this enum */ }; diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map index 20391ab..8b85ad8 100644 --- a/lib/ethdev/version.map +++ b/lib/ethdev/version.map @@ -279,6 +279,9 @@ EXPERIMENTAL { rte_flow_async_action_handle_create; rte_flow_async_action_handle_destroy; rte_flow_async_action_handle_update; + + # added in 22.07 + rte_eth_rx_queue_set_lwm; }; INTERNAL { -- 1.8.3.1