From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80369A0503; Sun, 8 May 2022 08:26:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2ACBD4069D; Sun, 8 May 2022 08:26:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D4CE740395 for ; Sun, 8 May 2022 08:26:24 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2485JSvH031119 for ; Sat, 7 May 2022 23:26:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=LV29XvMlk15CaxX0Vq5VppKx1Rc5/vtWIvi3DBhYbXs=; b=KPTuSwXbyf0O3s5eOjOQCVuvytWwCUXdbE4rsW+yIROxj8q76QT5dIm0SBgwuldfrMV6 dvUAQ496L1MPuCz3a+y+CtL1rrikN9o5HArRlR/0Ch4YGYyGoQgQzP+++nVM1oX89CLO hORB3+1YrXSDrZqAlhM0t4C8sgzAHzCVTmamtZN6vCS6lsbV5UyWkv8uhoaBgzOMXnw1 4pCFU5zOgAKHwfBJL+3JEQ23A7xZWFR69PrV5EQswqIN2R+IK1jT+TW57U9OKHSw0xAa BZMPJLcXSYMEue9LwhiMiOLdoVyfMHnTxnTRFHeAvd2/+38kyaLMtX7D+UEi9CXVI3zM sw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fwp4psymm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 07 May 2022 23:26:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 7 May 2022 23:26:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 7 May 2022 23:26:22 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D7D2A3F7053; Sat, 7 May 2022 23:26:19 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Subrahmanyam Nilla Subject: [PATCH v4 01/28] common/cnxk: add multi channel support for SDP send queues Date: Sun, 8 May 2022 11:55:49 +0530 Message-ID: <20220508062616.3398-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220419055921.10566-1-ndabilpuram@marvell.com> References: <20220419055921.10566-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: 5BOpGCbtWajvzVoQAjmAh3H4J7L5fpZi X-Proofpoint-GUID: 5BOpGCbtWajvzVoQAjmAh3H4J7L5fpZi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-08_02,2022-05-06_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Subrahmanyam Nilla Currently only base channel number is configured as default channel for all the SDP send queues. Due to this, packets sent on different SQ's are landing on the same output queue on the host. Channel number in the send queue should be configured according to the number of queues assigned to the SDP PF or VF device. Signed-off-by: Subrahmanyam Nilla --- v4: - Fixed build failure on RHEL with patch 28/28 v3: - Addressed comments from Jerin - Removed patch 26/28 and 27/28 due to functional issues - Added two more fixes. v2: - Fixed compilation issue with some compilers in patch 24/24 - Added few more fixes net/cnxk and related code in common/cnxk drivers/common/cnxk/roc_nix_queue.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 07dab4b..76c049c 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -706,6 +706,7 @@ static int sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, uint16_t smq) { + struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix); struct mbox *mbox = (&nix->dev)->mbox; struct nix_aq_enq_req *aq; @@ -721,7 +722,11 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.max_sqe_size = sq->max_sqe_sz; aq->sq.smq = smq; aq->sq.smq_rr_quantum = rr_quantum; - aq->sq.default_chan = nix->tx_chan_base; + if (roc_nix_is_sdp(roc_nix)) + aq->sq.default_chan = + nix->tx_chan_base + (sq->qid % nix->tx_chan_cnt); + else + aq->sq.default_chan = nix->tx_chan_base; aq->sq.sqe_stype = NIX_STYPE_STF; aq->sq.ena = 1; aq->sq.sso_ena = !!sq->sso_ena; -- 2.8.4