From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4D42A050C; Sun, 8 May 2022 09:48:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 852BE4069D; Sun, 8 May 2022 09:48:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9B3514068F for ; Sun, 8 May 2022 09:48:47 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2485HOkf023889 for ; Sun, 8 May 2022 00:48:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=kE6JEnj680iM9OvGDzUvTYKB58T9muhBFaGQJZOp1HE=; b=UDdX2nIZMLRhgHJy+q3YPwY46fnvB8/uls1w3GP1reHEncQYzCdlKPUJ+b4n6FWacfRL fddtwMXWwxywPkKzcNw+5SaLSsFpBYEtl2MVoDbbP/Gspa6s4ZE/BBIfWn0/Gd+cXmXq SbvInHzM2odt4ir+aYhgLWYXzHt6xm3MUn7zR6EiIDAPQjhOPp7d7HL48SSTFizqKnyK lcqFda3pj2B12NgPKc0yjIZ3z1EpWdNjzB18Y40876/UC97vlVnnTp9ZR0AviaL6lo+i ghc943+I0sjAmHSca582iW0Q3Q7NyfM1ym3QC9vahDa6Tf2meI2rhVhVVp+VZfP1y84O lQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fwp4pt5yv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 08 May 2022 00:48:46 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 8 May 2022 00:48:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 8 May 2022 00:48:44 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 9DEAD3F7050; Sun, 8 May 2022 00:48:42 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Subrahmanyam Nilla Subject: [PATCH v5 01/28] common/cnxk: add multi channel support for SDP send queues Date: Sun, 8 May 2022 13:18:12 +0530 Message-ID: <20220508074839.6965-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220419055921.10566-1-ndabilpuram@marvell.com> References: <20220419055921.10566-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: WVXM9N48YIubpPpCMJ4vcOZKY3_Okyyd X-Proofpoint-GUID: WVXM9N48YIubpPpCMJ4vcOZKY3_Okyyd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-08_02,2022-05-06_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Subrahmanyam Nilla Currently only base channel number is configured as default channel for all the SDP send queues. Due to this, packets sent on different SQ's are landing on the same output queue on the host. Channel number in the send queue should be configured according to the number of queues assigned to the SDP PF or VF device. Signed-off-by: Subrahmanyam Nilla --- v5: - Rebase and fix conflicts with dpdk-next-net-mrvl v4: - Fixed build failure on RHEL with patch 28/28 v3: - Addressed comments from Jerin - Removed patch 26/28 and 27/28 due to functional issues - Added two more fixes. v2: - Fixed compilation issue with some compilers in patch 24/24 - Added few more fixes net/cnxk and related code in common/cnxk drivers/common/cnxk/roc_nix_queue.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 07dab4b..76c049c 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -706,6 +706,7 @@ static int sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, uint16_t smq) { + struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix); struct mbox *mbox = (&nix->dev)->mbox; struct nix_aq_enq_req *aq; @@ -721,7 +722,11 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.max_sqe_size = sq->max_sqe_sz; aq->sq.smq = smq; aq->sq.smq_rr_quantum = rr_quantum; - aq->sq.default_chan = nix->tx_chan_base; + if (roc_nix_is_sdp(roc_nix)) + aq->sq.default_chan = + nix->tx_chan_base + (sq->qid % nix->tx_chan_cnt); + else + aq->sq.default_chan = nix->tx_chan_base; aq->sq.sqe_stype = NIX_STYPE_STF; aq->sq.ena = 1; aq->sq.sso_ena = !!sq->sso_ena; -- 2.8.4