From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 201D4A034C; Mon, 9 May 2022 12:19:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 069BD407FF; Mon, 9 May 2022 12:19:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0432C4068F for ; Mon, 9 May 2022 12:19:46 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 248NoROt009797; Mon, 9 May 2022 03:19:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6agdhVzEsRt8aPZv/0lwpBjPUctUCbc8EhwwcFs8zVg=; b=DFIJ3+RV/wbAXZk7mdD3XKGGExQUT5bmMDN8LfdH+FKZ6NfrmmdzIXrn+SxPHSC4/GWT hTkCHWg4zDX+D+cde5YWzUG7yeh/3jqVpOeRybDNXWTK4hXEyTJojYnXe1P1/nuBCUMz lgPVKwwzUXultpO9FEzlSSxEJ96yl+RlfJqf2699JN1EUAoCeu84hVO34xi7EAF6PrrJ VhQbn+5qKzRt8nS72fYMgqLM8ZHnsaJim0eY9EkltJeMcK/CSUdLslG6NDhAWEzN1xno 9DqqV3xzuHfzWgk6SCNG3wyMQmw1te99lBuwEXB63C0Jkaz+rfzftOFahHK2ddltQn4M Pg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fwp4pwx5n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 09 May 2022 03:19:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 9 May 2022 03:19:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 9 May 2022 03:19:42 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id 298A25B6921; Mon, 9 May 2022 03:19:39 -0700 (PDT) From: Rahul Bhansali To: , Ruifeng Wang , Jan Viktorin , Bruce Richardson CC: , Rahul Bhansali Subject: [PATCH v4 1/2] config/arm: add SVE ACLE control flag Date: Mon, 9 May 2022 15:49:31 +0530 Message-ID: <20220509101932.2403562-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505142744.1423344-1-rbhansali@marvell.com> References: <20220505142744.1423344-1-rbhansali@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: SftjIv7jwAnetnC1aU83prnH9HNBNUt0 X-Proofpoint-GUID: SftjIv7jwAnetnC1aU83prnH9HNBNUt0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-09_03,2022-05-09_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This add the control flag for SVE ACLE to enable or disable RTE_HAS_SVE_ACLE macro in the build. Signed-off-by: Rahul Bhansali --- Changes in v4: - Resend patches. With v3, patches were not sent properly in single series. Changes in v3: - Moved sve_acle condition to be consider for RTE_HAS_SVE_ACLE flag only. Changes in v2: - Renamed the flag to sve_acle from sve - Added double-indent. config/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 8aead74086..6f8961eac8 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -605,7 +605,7 @@ endif if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' compile_time_cpuflags += ['RTE_CPUFLAG_SVE'] - if (cc.check_header('arm_sve.h')) + if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle', true)) dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) endif endif -- 2.25.1