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From: Stephen Hemminger <stephen@networkplumber.org>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Stanislaw Kardach <kda@semihalf.com>,
	Thomas Monjalon <thomas@monjalon.net>,
	Michal Mazurek <maz@semihalf.com>,
	dev@dpdk.org, Frank Zhao <Frank.Zhao@starfivetech.com>,
	Sam Grove <sam.grove@sifive.com>,
	mw@semihalf.com, upstream@semihalf.com
Subject: Re: [PATCH v3 1/8] eal: add initial support for RISC-V architecture
Date: Fri, 13 May 2022 08:37:00 -0700	[thread overview]
Message-ID: <20220513083700.2b073882@hermes.local> (raw)
In-Reply-To: <7bc97240-10c7-c437-9f31-b97dc2b418c6@canonical.com>

On Fri, 13 May 2022 08:50:34 +0200
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote:

> On 5/10/22 17:48, Stanislaw Kardach wrote:
> > From: Michal Mazurek <maz@semihalf.com>
> > 
> > Add all necessary elements for DPDK to compile and run EAL on SiFive
> > Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
> > core complex.
> > 
> > This includes:
> > 
> > - EAL library implementation for rv64imafdc ISA.
> > - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
> >    is added for architecture identification.
> > - xmm_t structure operation stubs as there is no vector support in the
> >    U74 core.
> > 
> > Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
> > Clang compilation currently not supported due to issues with missing
> > relocation relaxation.
> > 
> > Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
> > (default) and unstable high-resolution using rdcycle. User can override
> > the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
> > both DPDK and the application. The reasoning for this is as follows.
> > The RISC-V ISA mandates that clock read by rdtime has to be of constant
> > period and synchronized between all hardware threads within 1 tick
> > (chapter 10.1 in version 20191213 of RISC-V spec).
> > However this clock may not be of high-enough frequency for dataplane
> > uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
> > There is a high-resolution alternative in form of rdcycle which is
> > clocked at the core clock frequency. The drawbacks are that it may be
> > disabled during sleep (WFI) and its frequency might change due to DVFS.

Choosing at compile time is ok for embedded but is undesireable for DPDK
in a distribution.  It sounds like the low-res is equivalent to hpet
and the unstable is same as x86 TSC. Therefore why not follow that
precedent and do the same thing?


  parent reply	other threads:[~2022-05-13 15:37 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 17:29 [PATCH 00/11] Introduce " Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 01/11] lpm: add a scalar version of lookupx4 function Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Stanislaw Kardach
2022-05-05 17:39   ` Stephen Hemminger
2022-05-05 17:49     ` Stanisław Kardach
2022-05-05 18:09       ` Stephen Hemminger
2022-05-05 17:29 ` [PATCH 03/11] eal: add initial support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 07/11] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 09/11] test/ring: disable problematic tests for RISC-V Stanislaw Kardach
2022-05-05 17:35   ` Stephen Hemminger
2022-05-05 17:43     ` Stanisław Kardach
2022-05-05 18:06       ` Stephen Hemminger
2022-05-10 23:28   ` Honnappa Nagarahalli
2022-05-11 10:07     ` Stanisław Kardach
2022-05-05 17:30 ` [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 11/11] test/hash: report non HTM numbers for single r/w Stanislaw Kardach
2022-05-06  9:13 ` [PATCH 00/11] Introduce support for RISC-V architecture David Marchand
2022-05-09 12:24   ` Stanisław Kardach
2022-05-09 12:30     ` Thomas Monjalon
2022-05-11  8:09       ` Morten Brørup
2022-05-11 10:28         ` Stanisław Kardach
2022-05-11 11:06           ` Thomas Monjalon
2022-05-09 14:30     ` David Marchand
2022-05-10 11:21       ` Stanisław Kardach
2022-05-10 12:31         ` Thomas Monjalon
2022-05-10 14:00           ` Stanisław Kardach
2022-05-10 14:23             ` Thomas Monjalon
2022-05-10 15:07 ` [PATCH v2 0/8] " Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 1/8] eal: add initial " Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:35     ` Stanisław Kardach
2022-05-10 15:07   ` [PATCH v2 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-10 15:48   ` [PATCH v3 0/8] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 1/8] eal: add initial " Stanislaw Kardach
2022-05-13  6:50       ` Heinrich Schuchardt
2022-05-13  8:42         ` Stanisław Kardach
2022-05-13 10:51           ` Heinrich Schuchardt
2022-05-13 11:47             ` Stanisław Kardach
2022-05-13 15:37         ` Stephen Hemminger [this message]
2022-05-16  8:00           ` Stanisław Kardach
2022-05-10 15:48     ` [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-12 15:47       ` Aaron Conole
2022-05-12 16:07         ` Stanisław Kardach
2022-05-13 14:33           ` Aaron Conole
2022-05-12  8:04 ` [PATCH 00/11] Introduce support for RISC-V architecture Heinrich Schuchardt
2022-05-12  8:35   ` Stanisław Kardach
2022-05-12  9:46     ` Heinrich Schuchardt
2022-05-12 13:56       ` Stanisław Kardach
2022-05-12 21:06         ` Heinrich Schuchardt

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