From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2DD5EA0503; Thu, 19 May 2022 11:37:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1ED8C40223; Thu, 19 May 2022 11:37:44 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id E8DB340156; Thu, 19 May 2022 11:37:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652953062; x=1684489062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SoBC8N5jHTK2sJt8USaeQczpoZcieuJQ6kTGFGqSYMk=; b=Don0x1pDEKs7ligX8ny+I/IW09oSJkhTsScn6k2vutw6VEyBvlHE1rRi xm341CauP0wIsEMTV9iBbf2Xel0VQ5RBPE5htHZqJu/UJNHlw8rJbbt2O FBWjePv3jtUFMZNvEC/ZwnwtlXjhcvgxjOYb/EqH9OTgIMCXEw87+Q468 MkZmygl+9viW9tP2WaqAnJVC2cAuBuPUBzueDIcsAjZS6mPnOZYkse3rd CMCsEC+QgH168tZSIcPm+0+6vnjle53IGl6E6Z9wyQ0HpyXrxIwRppqR5 iNqcow+yIxik+2LYPnanDhyigT7mz5qg4gulgxCw8jz5qQGEsNSBfA6dl A==; X-IronPort-AV: E=McAfee;i="6400,9594,10351"; a="272247062" X-IronPort-AV: E=Sophos;i="5.91,237,1647327600"; d="scan'208";a="272247062" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2022 02:37:41 -0700 X-IronPort-AV: E=Sophos;i="5.91,237,1647327600"; d="scan'208";a="714898481" Received: from unknown (HELO localhost.localdomain) ([10.239.251.104]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2022 02:37:39 -0700 From: Ke Zhang To: xiaoyun.li@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com, dev@dpdk.org Cc: Ke Zhang , stable@dpdk.org Subject: [PATCH v2] net/iavf: fix Rx queue interrupt setting Date: Thu, 19 May 2022 09:30:31 +0000 Message-Id: <20220519093031.256963-1-ke1x.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425083628.81133-1-ke1x.zhang@intel.com> References: <20220425083628.81133-1-ke1x.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For Rx-Queue Interrupt Setting, when vf rx interrupt disable(INTENA=0), there are two ways to write back descriptor to host memory: 1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register: Completed descriptors are posted to host memory according to the internal descriptor cache policy (in other words when a full cache line is available for write-back). 2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register: Completed descriptors also trigger the ITR. Following ITR expiration, all leftover completed descriptors are posted to host memory. Changing 1) to 2) to make sure VF synchronizing with PF. Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt") Cc: stable@dpdk.org Signed-off-by: Ke Zhang --- drivers/net/iavf/iavf_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d6190ac24a..17c7720600 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -1833,7 +1833,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START), - 0); + IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK); IAVF_WRITE_FLUSH(hw); return 0; -- 2.25.1