From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6DE2A0503; Fri, 20 May 2022 05:45:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 408F04114A; Fri, 20 May 2022 05:45:32 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id CB1B940151 for ; Fri, 20 May 2022 05:45:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653018331; x=1684554331; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sen2WusHv0Jy6RLGKkIodLE1p5lj9A8/kQYSQzn3Tjc=; b=ahbjWrw+HVIlyVFr2WXzdgMRKOI+yLROCrs/JnzGYQWOTj3nQwkBWv9M io1drb/Dh85XSA+v4TguJnimXgQ1DuC2DmHvk8x2QajoGxat1zFDkc/PV iq4bUOMROEukM5SH1jpDSlQ+qqLx6vnWoeb1jCAGqQ4b/HRkZ/ewD5Jy1 XVjJ9bgD5yyvc71M1U9saLWli8fkTIhCEVjENSydA+Bl70b+LTpzE5xyu PdUJyA+z3sVtWvl+uA6fiel9m6Pd08cJU6Z2SiYpIxYyPHTsZPEB8s7h3 v+yo9ejY/gWuZysMeDrkSawuEyLc5SGyEUFCA133JiLm7u3tKciuxr7M6 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10352"; a="272603024" X-IronPort-AV: E=Sophos;i="5.91,238,1647327600"; d="scan'208";a="272603024" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2022 20:43:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,238,1647327600"; d="scan'208";a="598980658" Received: from flexran-pae-icx01.an.intel.com (HELO pae-M50CYP2SBSTD.an.intel.com) ([10.123.100.83]) by orsmga008.jf.intel.com with ESMTP; 19 May 2022 20:43:45 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Subject: [PATCH v2 1/5] baseband/fpga_5gnr_fec: remove FLR timeout Date: Thu, 19 May 2022 22:05:52 -0500 Message-Id: <20220520030556.3475133-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520030556.3475133-1-hernan.vargas@intel.com> References: <20220520030556.3475133-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hernan FLR timeout register is not used in 5GNR FPGA. Signed-off-by: Hernan --- app/test-bbdev/test_bbdev_perf.c | 4 ---- drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 2 -- drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 9 --------- drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h | 2 -- 4 files changed, 17 deletions(-) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index 0fa119a502..fad3b1e49d 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -50,7 +50,6 @@ #define DL_5G_BANDWIDTH 3 #define UL_5G_LOAD_BALANCE 128 #define DL_5G_LOAD_BALANCE 128 -#define FLR_5G_TIMEOUT 610 #endif #ifdef RTE_BASEBAND_ACC100 @@ -699,9 +698,6 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info, conf.ul_load_balance = UL_5G_LOAD_BALANCE; conf.dl_load_balance = DL_5G_LOAD_BALANCE; - /**< FLR timeout value */ - conf.flr_time_out = FLR_5G_TIMEOUT; - /* setup FPGA PF with configuration information */ ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h index e72c95e936..ed8ce26eaa 100644 --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h @@ -36,7 +36,6 @@ #define FPGA_RING_DESC_LEN_UNIT_BYTES (32) /* Maximum size of queue */ #define FPGA_RING_MAX_SIZE (1024) -#define FPGA_FLR_TIMEOUT_UNIT (16.384) #define FPGA_NUM_UL_QUEUES (32) #define FPGA_NUM_DL_QUEUES (32) @@ -70,7 +69,6 @@ enum { FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */ FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */ FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */ - FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */ FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */ FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */ FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */ diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 15d23d6269..6737b74901 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -83,8 +83,6 @@ print_static_reg_debug_info(void *mmio_base) FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR); uint16_t ring_desc_len = fpga_reg_read_16(mmio_base, FPGA_5GNR_FEC_RING_DESC_LEN); - uint16_t flr_time_out = fpga_reg_read_16(mmio_base, - FPGA_5GNR_FEC_FLR_TIME_OUT); rte_bbdev_log_debug("UL.DL Weights = %u.%u", ((uint8_t)config), ((uint8_t)(config >> 8))); @@ -94,8 +92,6 @@ print_static_reg_debug_info(void *mmio_base) (qmap_done > 0) ? "READY" : "NOT-READY"); rte_bbdev_log_debug("Ring Descriptor Size = %u bytes", ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES); - rte_bbdev_log_debug("FLR Timeout = %f usec", - (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT); } /* Print decode DMA Descriptor of FPGA 5GNR Decoder device */ @@ -2120,11 +2116,6 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, address = FPGA_5GNR_FEC_RING_DESC_LEN; fpga_reg_write_16(d->mmio_base, address, payload_16); - /* Setting FLR timeout value */ - payload_16 = conf->flr_time_out; - address = FPGA_5GNR_FEC_FLR_TIME_OUT; - fpga_reg_write_16(d->mmio_base, address, payload_16); - /* Queue PF/VF mapping table is ready */ payload_8 = 0x1; address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE; diff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h index c2752fbd52..93a87c8e82 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h @@ -45,8 +45,6 @@ struct rte_fpga_5gnr_fec_conf { uint8_t ul_load_balance; /** DL Load Balance */ uint8_t dl_load_balance; - /** FLR timeout value */ - uint16_t flr_time_out; }; /** -- 2.25.1