From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53D9AA0544; Wed, 25 May 2022 05:21:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44D65427FF; Wed, 25 May 2022 05:20:57 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 09156427F9 for ; Wed, 25 May 2022 05:20:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653448852; x=1684984852; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6vsVvyUofWu2ZfWs2K9qEuJ2+okE4lqzqIpZDtWKvwY=; b=jIZm3CGvA+ykjNRWdGxsRk3AWn2wnJ/qJ4aVjmQWi0xoi0ZLEH4aOdQB iQGjU1fuJ61oIGTvR+Vzazmtw1UXc5yXSXTvod4mWK5LGIuxkCCoCs6ib t1o5Rw7PNh1uNL6LeCp3oAJPsdOVGINnj9pqgveWkw2dP+QOUUqhy4T27 Rgod8OwFzbSVJUNgZOXmLxBmyr/yvVODWnZFFeSBOxl9kavB9YfUb+0pB 3LYF+GZjS8y3SPQKV92q5GL6qN+m+2KV8Mjzoj+qnfb9cqpvlf8URF4oQ A09KFVLh99T9NkW6apMEnGZKrQL9pGXE/X7qfm8nopBPsaRGssEljgXpe A==; X-IronPort-AV: E=McAfee;i="6400,9594,10357"; a="299033892" X-IronPort-AV: E=Sophos;i="5.91,250,1647327600"; d="scan'208";a="299033892" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2022 20:20:51 -0700 X-IronPort-AV: E=Sophos;i="5.91,250,1647327600"; d="scan'208";a="601623601" Received: from intel-cd-odc-robin.cd.intel.com ([10.240.178.200]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2022 20:20:49 -0700 From: Robin Zhang To: dev@dpdk.org Cc: thomas@monjalon.net, andrew.rybchenko@oktetlabs.ru, kevinx.liu@intel.com, Robin Zhang Subject: [PATCH v8 5/5] ethdev: format module EEPROM for SFF-8636 Date: Wed, 25 May 2022 03:14:46 +0000 Message-Id: <20220525031446.72578-6-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220525031446.72578-1-robinx.zhang@intel.com> References: <20220524062442.194809-1-robinx.zhang@intel.com> <20220525031446.72578-1-robinx.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch implements format module EEPROM information for SFF-8636 Rev 2.7 Signed-off-by: Robin Zhang --- lib/ethdev/ethdev_sff_telemetry.c | 4 + lib/ethdev/meson.build | 1 + lib/ethdev/sff_8636.c | 750 ++++++++++++++++++++++++++++++ lib/ethdev/sff_8636.h | 611 ++++++++++++++++++++++++ 4 files changed, 1366 insertions(+) create mode 100644 lib/ethdev/sff_8636.c create mode 100644 lib/ethdev/sff_8636.h diff --git a/lib/ethdev/ethdev_sff_telemetry.c b/lib/ethdev/ethdev_sff_telemetry.c index c3b13b1cb1..b7d14219ef 100644 --- a/lib/ethdev/ethdev_sff_telemetry.c +++ b/lib/ethdev/ethdev_sff_telemetry.c @@ -77,6 +77,10 @@ sff_port_module_eeprom_parse(uint16_t port_id, struct rte_tel_data *d) sff_8079_show_all(einfo.data, d); sff_8472_show_all(einfo.data, d); break; + case RTE_ETH_MODULE_SFF_8436: + case RTE_ETH_MODULE_SFF_8636: + sff_8636_show_all(einfo.data, einfo.length, d); + break; default: RTE_ETHDEV_LOG(NOTICE, "Unsupported module type: %u\n", minfo.type); break; diff --git a/lib/ethdev/meson.build b/lib/ethdev/meson.build index 4d81a35c09..88ceeb12b9 100644 --- a/lib/ethdev/meson.build +++ b/lib/ethdev/meson.build @@ -15,6 +15,7 @@ sources = files( 'sff_common.c', 'sff_8079.c', 'sff_8472.c', + 'sff_8636.c', ) headers = files( diff --git a/lib/ethdev/sff_8636.c b/lib/ethdev/sff_8636.c new file mode 100644 index 0000000000..ad625fc73b --- /dev/null +++ b/lib/ethdev/sff_8636.c @@ -0,0 +1,750 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Intel Corporation + * + * Implements SFF-8636 based QSFP+/QSFP28 Diagnostics Memory map. + * + */ + +#include +#include +#include +#include +#include +#include "sff_common.h" +#include "sff_8636.h" +#include "ethdev_sff_telemetry.h" + +#define MAX_DESC_SIZE 42 + +static struct sff_8636_aw_flags { + const char *str; /* Human-readable string, null at the end */ + int offset; /* A2-relative address offset */ + uint8_t value; /* Alarm is on if (offset & value) != 0. */ +} sff_8636_aw_flags[] = { + { "Laser bias current high alarm (Chan 1)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_HALARM) }, + { "Laser bias current low alarm (Chan 1)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_LALARM) }, + { "Laser bias current high warning (Chan 1)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_HWARN) }, + { "Laser bias current low warning (Chan 1)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_LWARN) }, + + { "Laser bias current high alarm (Chan 2)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_HALARM) }, + { "Laser bias current low alarm (Chan 2)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_LALARM) }, + { "Laser bias current high warning (Chan 2)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_HWARN) }, + { "Laser bias current low warning (Chan 2)", + SFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_LWARN) }, + + { "Laser bias current high alarm (Chan 3)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_HALARM) }, + { "Laser bias current low alarm (Chan 3)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_LALARM) }, + { "Laser bias current high warning (Chan 3)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_HWARN) }, + { "Laser bias current low warning (Chan 3)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_LWARN) }, + + { "Laser bias current high alarm (Chan 4)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_HALARM) }, + { "Laser bias current low alarm (Chan 4)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_LALARM) }, + { "Laser bias current high warning (Chan 4)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_HWARN) }, + { "Laser bias current low warning (Chan 4)", + SFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_LWARN) }, + + { "Module temperature high alarm", + SFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_HALARM_STATUS) }, + { "Module temperature low alarm", + SFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_LALARM_STATUS) }, + { "Module temperature high warning", + SFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_HWARN_STATUS) }, + { "Module temperature low warning", + SFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_LWARN_STATUS) }, + + { "Module voltage high alarm", + SFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_HALARM_STATUS) }, + { "Module voltage low alarm", + SFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_LALARM_STATUS) }, + { "Module voltage high warning", + SFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_HWARN_STATUS) }, + { "Module voltage low warning", + SFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_LWARN_STATUS) }, + + { "Laser tx power high alarm (Channel 1)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_HALARM) }, + { "Laser tx power low alarm (Channel 1)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_LALARM) }, + { "Laser tx power high warning (Channel 1)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_HWARN) }, + { "Laser tx power low warning (Channel 1)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_LWARN) }, + + { "Laser tx power high alarm (Channel 2)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_HALARM) }, + { "Laser tx power low alarm (Channel 2)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_LALARM) }, + { "Laser tx power high warning (Channel 2)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_HWARN) }, + { "Laser tx power low warning (Channel 2)", + SFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_LWARN) }, + + { "Laser tx power high alarm (Channel 3)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_HALARM) }, + { "Laser tx power low alarm (Channel 3)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_LALARM) }, + { "Laser tx power high warning (Channel 3)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_HWARN) }, + { "Laser tx power low warning (Channel 3)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_LWARN) }, + + { "Laser tx power high alarm (Channel 4)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_HALARM) }, + { "Laser tx power low alarm (Channel 4)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_LALARM) }, + { "Laser tx power high warning (Channel 4)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_HWARN) }, + { "Laser tx power low warning (Channel 4)", + SFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_LWARN) }, + + { "Laser rx power high alarm (Channel 1)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_HALARM) }, + { "Laser rx power low alarm (Channel 1)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_LALARM) }, + { "Laser rx power high warning (Channel 1)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_HWARN) }, + { "Laser rx power low warning (Channel 1)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_LWARN) }, + + { "Laser rx power high alarm (Channel 2)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_HALARM) }, + { "Laser rx power low alarm (Channel 2)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_LALARM) }, + { "Laser rx power high warning (Channel 2)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_HWARN) }, + { "Laser rx power low warning (Channel 2)", + SFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_LWARN) }, + + { "Laser rx power high alarm (Channel 3)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_HALARM) }, + { "Laser rx power low alarm (Channel 3)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_LALARM) }, + { "Laser rx power high warning (Channel 3)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_HWARN) }, + { "Laser rx power low warning (Channel 3)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_LWARN) }, + + { "Laser rx power high alarm (Channel 4)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_HALARM) }, + { "Laser rx power low alarm (Channel 4)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_LALARM) }, + { "Laser rx power high warning (Channel 4)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_HWARN) }, + { "Laser rx power low warning (Channel 4)", + SFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_LWARN) }, + + { NULL, 0, 0 }, +}; + +static void sff_8636_show_identifier(const uint8_t *data, struct rte_tel_data *d) +{ + sff_8024_show_identifier(data, SFF_8636_ID_OFFSET, d); +} + +static void sff_8636_show_ext_identifier(const uint8_t *data, struct rte_tel_data *d) +{ + static const char *name = "Extended identifier description"; + char val_string[SFF_ITEM_VAL_COMPOSE_SIZE]; + snprintf(val_string, sizeof(val_string), "0x%02x", data[SFF_8636_EXT_ID_OFFSET]); + ssf_add_dict_string(d, "Extended identifier", val_string); + + switch (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_PWR_CLASS_MASK) { + case SFF_8636_EXT_ID_PWR_CLASS_1: + ssf_add_dict_string(d, name, "1.5W max. Power consumption"); + break; + case SFF_8636_EXT_ID_PWR_CLASS_2: + ssf_add_dict_string(d, name, "2.0W max. Power consumption"); + break; + case SFF_8636_EXT_ID_PWR_CLASS_3: + ssf_add_dict_string(d, name, "2.5W max. Power consumption"); + break; + case SFF_8636_EXT_ID_PWR_CLASS_4: + ssf_add_dict_string(d, name, "3.5W max. Power consumption"); + break; + } + + if (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_CDR_TX_MASK) + ssf_add_dict_string(d, name, "CDR present in TX"); + else + ssf_add_dict_string(d, name, "No CDR in TX"); + + if (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_CDR_RX_MASK) + ssf_add_dict_string(d, name, "CDR present in RX"); + else + ssf_add_dict_string(d, name, "No CDR in RX"); + + switch (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_EPWR_CLASS_MASK) { + case SFF_8636_EXT_ID_PWR_CLASS_LEGACY: + snprintf(val_string, sizeof(val_string), "%s", ""); + break; + case SFF_8636_EXT_ID_PWR_CLASS_5: + snprintf(val_string, sizeof(val_string), "%s", "4.0W max. Power consumption, "); + break; + case SFF_8636_EXT_ID_PWR_CLASS_6: + snprintf(val_string, sizeof(val_string), "%s", "4.5W max. Power consumption, "); + break; + case SFF_8636_EXT_ID_PWR_CLASS_7: + snprintf(val_string, sizeof(val_string), "%s", "5.0W max. Power consumption, "); + break; + } + + if (data[SFF_8636_PWR_MODE_OFFSET] & SFF_8636_HIGH_PWR_ENABLE) + strlcat(val_string, "High Power Class (> 3.5 W) enabled", sizeof(val_string)); + else + strlcat(val_string, "High Power Class (> 3.5 W) not enabled", sizeof(val_string)); + + ssf_add_dict_string(d, name, val_string); +} + +static void sff_8636_show_connector(const uint8_t *data, struct rte_tel_data *d) +{ + sff_8024_show_connector(data, SFF_8636_CTOR_OFFSET, d); +} + +static void sff_8636_show_transceiver(const uint8_t *data, struct rte_tel_data *d) +{ + static const char *name = "Transceiver type"; + char val_string[SFF_ITEM_VAL_COMPOSE_SIZE]; + + snprintf(val_string, sizeof(val_string), "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", + data[SFF_8636_ETHERNET_COMP_OFFSET], + data[SFF_8636_SONET_COMP_OFFSET], + data[SFF_8636_SAS_COMP_OFFSET], + data[SFF_8636_GIGE_COMP_OFFSET], + data[SFF_8636_FC_LEN_OFFSET], + data[SFF_8636_FC_TECH_OFFSET], + data[SFF_8636_FC_TRANS_MEDIA_OFFSET], + data[SFF_8636_FC_SPEED_OFFSET]); + ssf_add_dict_string(d, "Transceiver codes", val_string); + + /* 10G/40G Ethernet Compliance Codes */ + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_10G_LRM) + ssf_add_dict_string(d, name, "10G Ethernet: 10G Base-LRM"); + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_10G_LR) + ssf_add_dict_string(d, name, "10G Ethernet: 10G Base-LR"); + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_10G_SR) + ssf_add_dict_string(d, name, "10G Ethernet: 10G Base-SR"); + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_CR4) + ssf_add_dict_string(d, name, "40G Ethernet: 40G Base-CR4"); + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_SR4) + ssf_add_dict_string(d, name, "40G Ethernet: 40G Base-SR4"); + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_LR4) + ssf_add_dict_string(d, name, "40G Ethernet: 40G Base-LR4"); + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_ACTIVE) + ssf_add_dict_string(d, name, "40G Ethernet: 40G Active Cable (XLPPI)"); + + /* Extended Specification Compliance Codes from SFF-8024 */ + if (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_RSRVD) { + switch (data[SFF_8636_OPTION_1_OFFSET]) { + case SFF_8636_ETHERNET_UNSPECIFIED: + ssf_add_dict_string(d, name, "(reserved or unknown)"); + break; + case SFF_8636_ETHERNET_100G_AOC: + ssf_add_dict_string(d, name, + "100G Ethernet: 100G AOC or 25GAUI C2M AOC with worst BER of 5x10^(-5)"); + break; + case SFF_8636_ETHERNET_100G_SR4: + ssf_add_dict_string(d, name, + "100G Ethernet: 100G Base-SR4 or 25GBase-SR"); + break; + case SFF_8636_ETHERNET_100G_LR4: + ssf_add_dict_string(d, name, "100G Ethernet: 100G Base-LR4"); + break; + case SFF_8636_ETHERNET_100G_ER4: + ssf_add_dict_string(d, name, "100G Ethernet: 100G Base-ER4"); + break; + case SFF_8636_ETHERNET_100G_SR10: + ssf_add_dict_string(d, name, "100G Ethernet: 100G Base-SR10"); + break; + case SFF_8636_ETHERNET_100G_CWDM4_FEC: + ssf_add_dict_string(d, name, "100G Ethernet: 100G CWDM4 MSA with FEC"); + break; + case SFF_8636_ETHERNET_100G_PSM4: + ssf_add_dict_string(d, name, "100G Ethernet: 100G PSM4 Parallel SMF"); + break; + case SFF_8636_ETHERNET_100G_ACC: + ssf_add_dict_string(d, name, + "100G Ethernet: 100G ACC or 25GAUI C2M ACC with worst BER of 5x10^(-5)"); + break; + case SFF_8636_ETHERNET_100G_CWDM4_NO_FEC: + ssf_add_dict_string(d, name, + "100G Ethernet: 100G CWDM4 MSA without FEC"); + break; + case SFF_8636_ETHERNET_100G_RSVD1: + ssf_add_dict_string(d, name, "(reserved or unknown)"); + break; + case SFF_8636_ETHERNET_100G_CR4: + ssf_add_dict_string(d, name, + "100G Ethernet: 100G Base-CR4 or 25G Base-CR CA-L"); + break; + case SFF_8636_ETHERNET_25G_CR_CA_S: + ssf_add_dict_string(d, name, "25G Ethernet: 25G Base-CR CA-S"); + break; + case SFF_8636_ETHERNET_25G_CR_CA_N: + ssf_add_dict_string(d, name, "25G Ethernet: 25G Base-CR CA-N"); + break; + case SFF_8636_ETHERNET_40G_ER4: + ssf_add_dict_string(d, name, "40G Ethernet: 40G Base-ER4"); + break; + case SFF_8636_ETHERNET_4X10_SR: + ssf_add_dict_string(d, name, "4x10G Ethernet: 10G Base-SR"); + break; + case SFF_8636_ETHERNET_40G_PSM4: + ssf_add_dict_string(d, name, "40G Ethernet: 40G PSM4 Parallel SMF"); + break; + case SFF_8636_ETHERNET_G959_P1I1_2D1: + ssf_add_dict_string(d, name, + "Ethernet: G959.1 profile P1I1-2D1 (10709 MBd, 2km, 1310nm SM)"); + break; + case SFF_8636_ETHERNET_G959_P1S1_2D2: + ssf_add_dict_string(d, name, + "Ethernet: G959.1 profile P1S1-2D2 (10709 MBd, 40km, 1550nm SM)"); + break; + case SFF_8636_ETHERNET_G959_P1L1_2D2: + ssf_add_dict_string(d, name, + "Ethernet: G959.1 profile P1L1-2D2 (10709 MBd, 80km, 1550nm SM)"); + break; + case SFF_8636_ETHERNET_10GT_SFI: + ssf_add_dict_string(d, name, + "10G Ethernet: 10G Base-T with SFI electrical interface"); + break; + case SFF_8636_ETHERNET_100G_CLR4: + ssf_add_dict_string(d, name, "100G Ethernet: 100G CLR4"); + break; + case SFF_8636_ETHERNET_100G_AOC2: + ssf_add_dict_string(d, name, + "100G Ethernet: 100G AOC or 25GAUI C2M AOC with worst BER of 10^(-12)"); + break; + case SFF_8636_ETHERNET_100G_ACC2: + ssf_add_dict_string(d, name, + "100G Ethernet: 100G ACC or 25GAUI C2M ACC with worst BER of 10^(-12)"); + break; + default: + ssf_add_dict_string(d, name, "(reserved or unknown)"); + break; + } + } + + /* SONET Compliance Codes */ + if (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_40G_OTN) + ssf_add_dict_string(d, name, "40G OTN (OTU3B/OTU3C)"); + if (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_OC48_LR) + ssf_add_dict_string(d, name, "SONET: OC-48, long reach"); + if (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_OC48_IR) + ssf_add_dict_string(d, name, "SONET: OC-48, intermediate reach"); + if (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_OC48_SR) + ssf_add_dict_string(d, name, "SONET: OC-48, short reach"); + + /* SAS/SATA Compliance Codes */ + if (data[SFF_8636_SAS_COMP_OFFSET] & SFF_8636_SAS_6G) + ssf_add_dict_string(d, name, "SAS 6.0G"); + if (data[SFF_8636_SAS_COMP_OFFSET] & SFF_8636_SAS_3G) + ssf_add_dict_string(d, name, "SAS 3.0G"); + + /* Ethernet Compliance Codes */ + if (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_T) + ssf_add_dict_string(d, name, "Ethernet: 1000BASE-T"); + if (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_CX) + ssf_add_dict_string(d, name, "Ethernet: 1000BASE-CX"); + if (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_LX) + ssf_add_dict_string(d, name, "Ethernet: 1000BASE-LX"); + if (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_SX) + ssf_add_dict_string(d, name, "Ethernet: 1000BASE-SX"); + + /* Fibre Channel link length */ + if (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_VERY_LONG) + ssf_add_dict_string(d, name, "FC: very long distance (V)"); + if (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_SHORT) + ssf_add_dict_string(d, name, "FC: short distance (S)"); + if (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_INT) + ssf_add_dict_string(d, name, "FC: intermediate distance (I)"); + if (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_LONG) + ssf_add_dict_string(d, name, "FC: long distance (L)"); + if (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_MED) + ssf_add_dict_string(d, name, "FC: medium distance (M)"); + + /* Fibre Channel transmitter technology */ + if (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_TECH_LONG_LC) + ssf_add_dict_string(d, name, "FC: Longwave laser (LC)"); + if (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_TECH_ELEC_INTER) + ssf_add_dict_string(d, name, "FC: Electrical inter-enclosure (EL)"); + if (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_ELEC_INTRA) + ssf_add_dict_string(d, name, "FC: Electrical intra-enclosure (EL)"); + if (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_SHORT_WO_OFC) + ssf_add_dict_string(d, name, "FC: Shortwave laser w/o OFC (SN)"); + if (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_SHORT_W_OFC) + ssf_add_dict_string(d, name, "FC: Shortwave laser with OFC (SL)"); + if (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_LONG_LL) + ssf_add_dict_string(d, name, "FC: Longwave laser (LL)"); + + /* Fibre Channel transmission media */ + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_TW) + ssf_add_dict_string(d, name, "FC: Twin Axial Pair (TW)"); + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_TP) + ssf_add_dict_string(d, name, "FC: Twisted Pair (TP)"); + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_MI) + ssf_add_dict_string(d, name, "FC: Miniature Coax (MI)"); + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_TV) + ssf_add_dict_string(d, name, "FC: Video Coax (TV)"); + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_M6) + ssf_add_dict_string(d, name, "FC: Multimode, 62.5m (M6)"); + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_M5) + ssf_add_dict_string(d, name, "FC: Multimode, 50m (M5)"); + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_OM3) + ssf_add_dict_string(d, name, "FC: Multimode, 50um (OM3)"); + if (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_SM) + ssf_add_dict_string(d, name, "FC: Single Mode (SM)"); + + /* Fibre Channel speed */ + if (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_1200_MBPS) + ssf_add_dict_string(d, name, "FC: 1200 MBytes/sec"); + if (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_800_MBPS) + ssf_add_dict_string(d, name, "FC: 800 MBytes/sec"); + if (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_1600_MBPS) + ssf_add_dict_string(d, name, "FC: 1600 MBytes/sec"); + if (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_400_MBPS) + ssf_add_dict_string(d, name, "FC: 400 MBytes/sec"); + if (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_200_MBPS) + ssf_add_dict_string(d, name, "FC: 200 MBytes/sec"); + if (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_100_MBPS) + ssf_add_dict_string(d, name, "FC: 100 MBytes/sec"); +} + +static void sff_8636_show_encoding(const uint8_t *data, struct rte_tel_data *d) +{ + sff_8024_show_encoding(data, SFF_8636_ENCODING_OFFSET, + RTE_ETH_MODULE_SFF_8636, d); +} + +static void sff_8636_show_rate_identifier(const uint8_t *data, struct rte_tel_data *d) +{ + char val_string[20]; + + snprintf(val_string, sizeof(val_string), "0x%02x", data[SFF_8636_EXT_RS_OFFSET]); + ssf_add_dict_string(d, "Rate identifier", val_string); +} + +static void sff_8636_show_oui(const uint8_t *data, struct rte_tel_data *d) +{ + sff_8024_show_oui(data, SFF_8636_VENDOR_OUI_OFFSET, d); +} + +static void sff_8636_show_wavelength_or_copper_compliance(const uint8_t *data, + struct rte_tel_data *d) +{ + char val_string[SFF_ITEM_VAL_COMPOSE_SIZE]; + snprintf(val_string, sizeof(val_string), "0x%02x", + (data[SFF_8636_DEVICE_TECH_OFFSET] & SFF_8636_TRANS_TECH_MASK)); + + switch (data[SFF_8636_DEVICE_TECH_OFFSET] & SFF_8636_TRANS_TECH_MASK) { + case SFF_8636_TRANS_850_VCSEL: + strlcat(val_string, " (850 nm VCSEL)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1310_VCSEL: + strlcat(val_string, " (1310 nm VCSEL)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1550_VCSEL: + strlcat(val_string, " (1550 nm VCSEL)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1310_FP: + strlcat(val_string, " (1310 nm FP)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1310_DFB: + strlcat(val_string, " (1310 nm DFB)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1550_DFB: + strlcat(val_string, " (1550 nm DFB)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1310_EML: + strlcat(val_string, " (1310 nm EML)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1550_EML: + strlcat(val_string, " (1550 nm EML)", sizeof(val_string)); + break; + case SFF_8636_TRANS_OTHERS: + strlcat(val_string, " (Others/Undefined)", sizeof(val_string)); + break; + case SFF_8636_TRANS_1490_DFB: + strlcat(val_string, " (1490 nm DFB)", sizeof(val_string)); + break; + case SFF_8636_TRANS_COPPER_PAS_UNEQUAL: + strlcat(val_string, " (Copper cable unequalized)", sizeof(val_string)); + break; + case SFF_8636_TRANS_COPPER_PAS_EQUAL: + strlcat(val_string, " (Copper cable passive equalized)", sizeof(val_string)); + break; + case SFF_8636_TRANS_COPPER_LNR_FAR_EQUAL: + strlcat(val_string, + " (Copper cable, near and far end limiting active equalizers)", + sizeof(val_string)); + break; + case SFF_8636_TRANS_COPPER_FAR_EQUAL: + strlcat(val_string, + " (Copper cable, far end limiting active equalizers)", + sizeof(val_string)); + break; + case SFF_8636_TRANS_COPPER_NEAR_EQUAL: + strlcat(val_string, + " (Copper cable, near end limiting active equalizers)", + sizeof(val_string)); + break; + case SFF_8636_TRANS_COPPER_LNR_EQUAL: + strlcat(val_string, + " (Copper cable, linear active equalizers)", + sizeof(val_string)); + break; + } + ssf_add_dict_string(d, "Transmitter technology", val_string); + + if ((data[SFF_8636_DEVICE_TECH_OFFSET] & SFF_8636_TRANS_TECH_MASK) + >= SFF_8636_TRANS_COPPER_PAS_UNEQUAL) { + snprintf(val_string, sizeof(val_string), "%udb", + data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]); + ssf_add_dict_string(d, "Attenuation at 2.5GHz", val_string); + + snprintf(val_string, sizeof(val_string), "%udb", + data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]); + ssf_add_dict_string(d, "Attenuation at 5.0GHz", val_string); + + snprintf(val_string, sizeof(val_string), "%udb", + data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]); + ssf_add_dict_string(d, "Attenuation at 7.0GHz", val_string); + + snprintf(val_string, sizeof(val_string), "%udb", + data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]); + ssf_add_dict_string(d, "Attenuation at 12.9GHz", val_string); + } else { + snprintf(val_string, sizeof(val_string), "%.3lfnm", + (((data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET] << 8) | + data[SFF_8636_WAVELEN_LOW_BYTE_OFFSET])*0.05)); + ssf_add_dict_string(d, "Laser wavelength", val_string); + + snprintf(val_string, sizeof(val_string), "%.3lfnm", + (((data[SFF_8636_WAVE_TOL_HIGH_BYTE_OFFSET] << 8) | + data[SFF_8636_WAVE_TOL_LOW_BYTE_OFFSET])*0.005)); + ssf_add_dict_string(d, "Laser wavelength tolerance", val_string); + } +} + +static void sff_8636_show_revision_compliance(const uint8_t *data, struct rte_tel_data *d) +{ + static const char *name = "Revision Compliance"; + + switch (data[SFF_8636_REV_COMPLIANCE_OFFSET]) { + case SFF_8636_REV_UNSPECIFIED: + ssf_add_dict_string(d, name, "Revision not specified"); + break; + case SFF_8636_REV_8436_48: + ssf_add_dict_string(d, name, "SFF-8436 Rev 4.8 or earlier"); + break; + case SFF_8636_REV_8436_8636: + ssf_add_dict_string(d, name, "SFF-8436 Rev 4.8 or earlier"); + break; + case SFF_8636_REV_8636_13: + ssf_add_dict_string(d, name, "SFF-8636 Rev 1.3 or earlier"); + break; + case SFF_8636_REV_8636_14: + ssf_add_dict_string(d, name, "SFF-8636 Rev 1.4"); + break; + case SFF_8636_REV_8636_15: + ssf_add_dict_string(d, name, "SFF-8636 Rev 1.5"); + break; + case SFF_8636_REV_8636_20: + ssf_add_dict_string(d, name, "SFF-8636 Rev 2.0"); + break; + case SFF_8636_REV_8636_27: + ssf_add_dict_string(d, name, "SFF-8636 Rev 2.5/2.6/2.7"); + break; + default: + ssf_add_dict_string(d, name, "Unallocated"); + break; + } +} + +/* + * 2-byte internal temperature conversions: + * First byte is a signed 8-bit integer, which is the temp decimal part + * Second byte are 1/256th of degree, which are added to the dec part. + */ +#define SFF_8636_OFFSET_TO_TEMP(offset) ((int16_t)OFFSET_TO_U16(offset)) + +static void sff_8636_dom_parse(const uint8_t *data, struct sff_diags *sd) +{ + int i = 0; + + /* Monitoring Thresholds for Alarms and Warnings */ + sd->sfp_voltage[MCURR] = OFFSET_TO_U16(SFF_8636_VCC_CURR); + sd->sfp_voltage[HALRM] = OFFSET_TO_U16(SFF_8636_VCC_HALRM); + sd->sfp_voltage[LALRM] = OFFSET_TO_U16(SFF_8636_VCC_LALRM); + sd->sfp_voltage[HWARN] = OFFSET_TO_U16(SFF_8636_VCC_HWARN); + sd->sfp_voltage[LWARN] = OFFSET_TO_U16(SFF_8636_VCC_LWARN); + + sd->sfp_temp[MCURR] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_CURR); + sd->sfp_temp[HALRM] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_HALRM); + sd->sfp_temp[LALRM] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_LALRM); + sd->sfp_temp[HWARN] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_HWARN); + sd->sfp_temp[LWARN] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_LWARN); + + sd->bias_cur[HALRM] = OFFSET_TO_U16(SFF_8636_TX_BIAS_HALRM); + sd->bias_cur[LALRM] = OFFSET_TO_U16(SFF_8636_TX_BIAS_LALRM); + sd->bias_cur[HWARN] = OFFSET_TO_U16(SFF_8636_TX_BIAS_HWARN); + sd->bias_cur[LWARN] = OFFSET_TO_U16(SFF_8636_TX_BIAS_LWARN); + + sd->tx_power[HALRM] = OFFSET_TO_U16(SFF_8636_TX_PWR_HALRM); + sd->tx_power[LALRM] = OFFSET_TO_U16(SFF_8636_TX_PWR_LALRM); + sd->tx_power[HWARN] = OFFSET_TO_U16(SFF_8636_TX_PWR_HWARN); + sd->tx_power[LWARN] = OFFSET_TO_U16(SFF_8636_TX_PWR_LWARN); + + sd->rx_power[HALRM] = OFFSET_TO_U16(SFF_8636_RX_PWR_HALRM); + sd->rx_power[LALRM] = OFFSET_TO_U16(SFF_8636_RX_PWR_LALRM); + sd->rx_power[HWARN] = OFFSET_TO_U16(SFF_8636_RX_PWR_HWARN); + sd->rx_power[LWARN] = OFFSET_TO_U16(SFF_8636_RX_PWR_LWARN); + + + /* Channel Specific Data */ + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + sd->scd[i].bias_cur = OFFSET_TO_U16(tx_bias_offset[i]); + sd->scd[i].rx_power = OFFSET_TO_U16(rx_power_offset[i]); + sd->scd[i].tx_power = OFFSET_TO_U16(tx_power_offset[i]); + } + +} + +static void sff_8636_show_dom(const uint8_t *data, uint32_t eeprom_len, struct rte_tel_data *d) +{ + struct sff_diags sd = {0}; + const char *rx_power_string = NULL; + char power_string[MAX_DESC_SIZE]; + char val_string[SFF_ITEM_VAL_COMPOSE_SIZE]; + int i; + + /* + * There is no clear identifier to signify the existence of + * optical diagnostics similar to SFF-8472. So checking existence + * of page 3, will provide the gurantee for existence of alarms + * and thresholds + * If pagging support exists, then supports_alarms is marked as 1 + */ + + if (eeprom_len == RTE_ETH_MODULE_SFF_8636_MAX_LEN) { + if (!(data[SFF_8636_STATUS_2_OFFSET] & + SFF_8636_STATUS_PAGE_3_PRESENT)) { + sd.supports_alarms = 1; + } + } + + sd.rx_power_type = data[SFF_8636_DIAG_TYPE_OFFSET] & + SFF_8636_RX_PWR_TYPE_MASK; + sd.tx_power_type = data[SFF_8636_DIAG_TYPE_OFFSET] & + SFF_8636_RX_PWR_TYPE_MASK; + + sff_8636_dom_parse(data, &sd); + + SPRINT_TEMP(val_string, sd.sfp_temp[MCURR]); + ssf_add_dict_string(d, "Module temperature", val_string); + + SPRINT_VCC(val_string, sd.sfp_voltage[MCURR]); + ssf_add_dict_string(d, "Module voltage", val_string); + + /* + * SFF-8636/8436 spec is not clear whether RX power/ TX bias + * current fields are supported or not. A valid temperature + * reading is used as existence for TX/RX power. + */ + if ((sd.sfp_temp[MCURR] == 0x0) || + (sd.sfp_temp[MCURR] == (int16_t)0xFFFF)) + return; + + ssf_add_dict_string(d, "Alarm/warning flags implemented", + (sd.supports_alarms ? "Yes" : "No")); + + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + snprintf(power_string, MAX_DESC_SIZE, "%s (Channel %d)", + "Laser tx bias current", i+1); + SPRINT_BIAS(val_string, sd.scd[i].bias_cur); + ssf_add_dict_string(d, power_string, val_string); + } + + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + snprintf(power_string, MAX_DESC_SIZE, "%s (Channel %d)", + "Transmit avg optical power", i+1); + SPRINT_xX_PWR(val_string, sd.scd[i].tx_power); + ssf_add_dict_string(d, power_string, val_string); + } + + if (!sd.rx_power_type) + rx_power_string = "Receiver signal OMA"; + else + rx_power_string = "Rcvr signal avg optical power"; + + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + snprintf(power_string, MAX_DESC_SIZE, "%s(Channel %d)", + rx_power_string, i+1); + SPRINT_xX_PWR(val_string, sd.scd[i].rx_power); + ssf_add_dict_string(d, power_string, val_string); + } + + if (sd.supports_alarms) { + for (i = 0; sff_8636_aw_flags[i].str; ++i) { + ssf_add_dict_string(d, sff_8636_aw_flags[i].str, + data[sff_8636_aw_flags[i].offset] + & sff_8636_aw_flags[i].value ? "On" : "Off"); + } + + sff_show_thresholds(sd, d); + } + +} +void sff_8636_show_all(const uint8_t *data, uint32_t eeprom_len, struct rte_tel_data *d) +{ + sff_8636_show_identifier(data, d); + if ((data[SFF_8636_ID_OFFSET] == SFF_8024_ID_QSFP) || + (data[SFF_8636_ID_OFFSET] == SFF_8024_ID_QSFP_PLUS) || + (data[SFF_8636_ID_OFFSET] == SFF_8024_ID_QSFP28)) { + sff_8636_show_ext_identifier(data, d); + sff_8636_show_connector(data, d); + sff_8636_show_transceiver(data, d); + sff_8636_show_encoding(data, d); + sff_show_value_with_unit(data, SFF_8636_BR_NOMINAL_OFFSET, + "BR, Nominal", 100, "Mbps", d); + sff_8636_show_rate_identifier(data, d); + sff_show_value_with_unit(data, SFF_8636_SM_LEN_OFFSET, + "Length (SMF,km)", 1, "km", d); + sff_show_value_with_unit(data, SFF_8636_OM3_LEN_OFFSET, + "Length (OM3 50um)", 2, "m", d); + sff_show_value_with_unit(data, SFF_8636_OM2_LEN_OFFSET, + "Length (OM2 50um)", 1, "m", d); + sff_show_value_with_unit(data, SFF_8636_OM1_LEN_OFFSET, + "Length (OM1 62.5um)", 1, "m", d); + sff_show_value_with_unit(data, SFF_8636_CBL_LEN_OFFSET, + "Length (Copper or Active cable)", 1, "m", d); + sff_8636_show_wavelength_or_copper_compliance(data, d); + sff_show_ascii(data, SFF_8636_VENDOR_NAME_START_OFFSET, + SFF_8636_VENDOR_NAME_END_OFFSET, "Vendor name", d); + sff_8636_show_oui(data, d); + sff_show_ascii(data, SFF_8636_VENDOR_PN_START_OFFSET, + SFF_8636_VENDOR_PN_END_OFFSET, "Vendor PN", d); + sff_show_ascii(data, SFF_8636_VENDOR_REV_START_OFFSET, + SFF_8636_VENDOR_REV_END_OFFSET, "Vendor rev", d); + sff_show_ascii(data, SFF_8636_VENDOR_SN_START_OFFSET, + SFF_8636_VENDOR_SN_END_OFFSET, "Vendor SN", d); + sff_show_ascii(data, SFF_8636_DATE_YEAR_OFFSET, + SFF_8636_DATE_VENDOR_LOT_OFFSET + 1, "Date code", d); + sff_8636_show_revision_compliance(data, d); + sff_8636_show_dom(data, eeprom_len, d); + } +} diff --git a/lib/ethdev/sff_8636.h b/lib/ethdev/sff_8636.h new file mode 100644 index 0000000000..49e5feb35f --- /dev/null +++ b/lib/ethdev/sff_8636.h @@ -0,0 +1,611 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Intel Corporation + * + * SFF-8636 standards based QSFP EEPROM Field Definitions + * + */ + +#ifndef _SFF_8636_H_ +#define _SFF_8636_H_ + +/*------------------------------------------------------------------------------ + * + * QSFP EEPROM data structures + * + * register info from SFF-8636 Rev 2.7 + */ + +/*------------------------------------------------------------------------------ + * + * Lower Memory Page 00h + * Measurement, Diagnostic and Control Functions + * + */ +/* Identifier - 0 */ +/* Values are defined under SFF_8024_ID_OFFSET */ +#define SFF_8636_ID_OFFSET 0x00 + +#define SFF_8636_REV_COMPLIANCE_OFFSET 0x01 +#define SFF_8636_REV_UNSPECIFIED 0x00 +#define SFF_8636_REV_8436_48 0x01 +#define SFF_8636_REV_8436_8636 0x02 +#define SFF_8636_REV_8636_13 0x03 +#define SFF_8636_REV_8636_14 0x04 +#define SFF_8636_REV_8636_15 0x05 +#define SFF_8636_REV_8636_20 0x06 +#define SFF_8636_REV_8636_27 0x07 + +#define SFF_8636_STATUS_2_OFFSET 0x02 +/* Flat Memory:0- Paging, 1- Page 0 only */ +#define SFF_8636_STATUS_PAGE_3_PRESENT (1 << 2) +#define SFF_8636_STATUS_INTL_OUTPUT (1 << 1) +#define SFF_8636_STATUS_DATA_NOT_READY (1 << 0) + +/* Channel Status Interrupt Flags - 3-5 */ +#define SFF_8636_LOS_AW_OFFSET 0x03 +#define SFF_8636_TX4_LOS_AW (1 << 7) +#define SFF_8636_TX3_LOS_AW (1 << 6) +#define SFF_8636_TX2_LOS_AW (1 << 5) +#define SFF_8636_TX1_LOS_AW (1 << 4) +#define SFF_8636_RX4_LOS_AW (1 << 3) +#define SFF_8636_RX3_LOS_AW (1 << 2) +#define SFF_8636_RX2_LOS_AW (1 << 1) +#define SFF_8636_RX1_LOS_AW (1 << 0) + +#define SFF_8636_FAULT_AW_OFFSET 0x04 +#define SFF_8636_TX4_FAULT_AW (1 << 3) +#define SFF_8636_TX3_FAULT_AW (1 << 2) +#define SFF_8636_TX2_FAULT_AW (1 << 1) +#define SFF_8636_TX1_FAULT_AW (1 << 0) + +/* Module Monitor Interrupt Flags - 6-8 */ +#define SFF_8636_TEMP_AW_OFFSET 0x06 +#define SFF_8636_TEMP_HALARM_STATUS (1 << 7) +#define SFF_8636_TEMP_LALARM_STATUS (1 << 6) +#define SFF_8636_TEMP_HWARN_STATUS (1 << 5) +#define SFF_8636_TEMP_LWARN_STATUS (1 << 4) + +#define SFF_8636_VCC_AW_OFFSET 0x07 +#define SFF_8636_VCC_HALARM_STATUS (1 << 7) +#define SFF_8636_VCC_LALARM_STATUS (1 << 6) +#define SFF_8636_VCC_HWARN_STATUS (1 << 5) +#define SFF_8636_VCC_LWARN_STATUS (1 << 4) + +/* Channel Monitor Interrupt Flags - 9-21 */ +#define SFF_8636_RX_PWR_12_AW_OFFSET 0x09 +#define SFF_8636_RX_PWR_1_HALARM (1 << 7) +#define SFF_8636_RX_PWR_1_LALARM (1 << 6) +#define SFF_8636_RX_PWR_1_HWARN (1 << 5) +#define SFF_8636_RX_PWR_1_LWARN (1 << 4) +#define SFF_8636_RX_PWR_2_HALARM (1 << 3) +#define SFF_8636_RX_PWR_2_LALARM (1 << 2) +#define SFF_8636_RX_PWR_2_HWARN (1 << 1) +#define SFF_8636_RX_PWR_2_LWARN (1 << 0) + +#define SFF_8636_RX_PWR_34_AW_OFFSET 0x0A +#define SFF_8636_RX_PWR_3_HALARM (1 << 7) +#define SFF_8636_RX_PWR_3_LALARM (1 << 6) +#define SFF_8636_RX_PWR_3_HWARN (1 << 5) +#define SFF_8636_RX_PWR_3_LWARN (1 << 4) +#define SFF_8636_RX_PWR_4_HALARM (1 << 3) +#define SFF_8636_RX_PWR_4_LALARM (1 << 2) +#define SFF_8636_RX_PWR_4_HWARN (1 << 1) +#define SFF_8636_RX_PWR_4_LWARN (1 << 0) + +#define SFF_8636_TX_BIAS_12_AW_OFFSET 0x0B +#define SFF_8636_TX_BIAS_1_HALARM (1 << 7) +#define SFF_8636_TX_BIAS_1_LALARM (1 << 6) +#define SFF_8636_TX_BIAS_1_HWARN (1 << 5) +#define SFF_8636_TX_BIAS_1_LWARN (1 << 4) +#define SFF_8636_TX_BIAS_2_HALARM (1 << 3) +#define SFF_8636_TX_BIAS_2_LALARM (1 << 2) +#define SFF_8636_TX_BIAS_2_HWARN (1 << 1) +#define SFF_8636_TX_BIAS_2_LWARN (1 << 0) + +#define SFF_8636_TX_BIAS_34_AW_OFFSET 0xC +#define SFF_8636_TX_BIAS_3_HALARM (1 << 7) +#define SFF_8636_TX_BIAS_3_LALARM (1 << 6) +#define SFF_8636_TX_BIAS_3_HWARN (1 << 5) +#define SFF_8636_TX_BIAS_3_LWARN (1 << 4) +#define SFF_8636_TX_BIAS_4_HALARM (1 << 3) +#define SFF_8636_TX_BIAS_4_LALARM (1 << 2) +#define SFF_8636_TX_BIAS_4_HWARN (1 << 1) +#define SFF_8636_TX_BIAS_4_LWARN (1 << 0) + +#define SFF_8636_TX_PWR_12_AW_OFFSET 0x0D +#define SFF_8636_TX_PWR_1_HALARM (1 << 7) +#define SFF_8636_TX_PWR_1_LALARM (1 << 6) +#define SFF_8636_TX_PWR_1_HWARN (1 << 5) +#define SFF_8636_TX_PWR_1_LWARN (1 << 4) +#define SFF_8636_TX_PWR_2_HALARM (1 << 3) +#define SFF_8636_TX_PWR_2_LALARM (1 << 2) +#define SFF_8636_TX_PWR_2_HWARN (1 << 1) +#define SFF_8636_TX_PWR_2_LWARN (1 << 0) + +#define SFF_8636_TX_PWR_34_AW_OFFSET 0x0E +#define SFF_8636_TX_PWR_3_HALARM (1 << 7) +#define SFF_8636_TX_PWR_3_LALARM (1 << 6) +#define SFF_8636_TX_PWR_3_HWARN (1 << 5) +#define SFF_8636_TX_PWR_3_LWARN (1 << 4) +#define SFF_8636_TX_PWR_4_HALARM (1 << 3) +#define SFF_8636_TX_PWR_4_LALARM (1 << 2) +#define SFF_8636_TX_PWR_4_HWARN (1 << 1) +#define SFF_8636_TX_PWR_4_LWARN (1 << 0) + +/* Module Monitoring Values - 22-33 */ +#define SFF_8636_TEMP_CURR 0x16 +#define SFF_8636_TEMP_MSB_OFFSET 0x16 +#define SFF_8636_TEMP_LSB_OFFSET 0x17 + +#define SFF_8636_VCC_CURR 0x1A +#define SFF_8636_VCC_MSB_OFFSET 0x1A +#define SFF_8636_VCC_LSB_OFFSET 0x1B + +/* Channel Monitoring Values - 34-81 */ +#define SFF_8636_RX_PWR_1_OFFSET 0x22 +#define SFF_8636_RX_PWR_2_OFFSET 0x24 +#define SFF_8636_RX_PWR_3_OFFSET 0x26 +#define SFF_8636_RX_PWR_4_OFFSET 0x28 + +#define SFF_8636_TX_BIAS_1_OFFSET 0x2A +#define SFF_8636_TX_BIAS_2_OFFSET 0x2C +#define SFF_8636_TX_BIAS_3_OFFSET 0x2E +#define SFF_8636_TX_BIAS_4_OFFSET 0x30 + +#define SFF_8636_TX_PWR_1_OFFSET 0x32 +#define SFF_8636_TX_PWR_2_OFFSET 0x34 +#define SFF_8636_TX_PWR_3_OFFSET 0x36 +#define SFF_8636_TX_PWR_4_OFFSET 0x38 + +/* Control Bytes - 86 - 99 */ +#define SFF_8636_TX_DISABLE_OFFSET 0x56 +#define SFF_8636_TX_DISABLE_4 (1 << 3) +#define SFF_8636_TX_DISABLE_3 (1 << 2) +#define SFF_8636_TX_DISABLE_2 (1 << 1) +#define SFF_8636_TX_DISABLE_1 (1 << 0) + +#define SFF_8636_RX_RATE_SELECT_OFFSET 0x57 +#define SFF_8636_RX_RATE_SELECT_4_MASK (3 << 6) +#define SFF_8636_RX_RATE_SELECT_3_MASK (3 << 4) +#define SFF_8636_RX_RATE_SELECT_2_MASK (3 << 2) +#define SFF_8636_RX_RATE_SELECT_1_MASK (3 << 0) + +#define SFF_8636_TX_RATE_SELECT_OFFSET 0x58 +#define SFF_8636_TX_RATE_SELECT_4_MASK (3 << 6) +#define SFF_8636_TX_RATE_SELECT_3_MASK (3 << 4) +#define SFF_8636_TX_RATE_SELECT_2_MASK (3 << 2) +#define SFF_8636_TX_RATE_SELECT_1_MASK (3 << 0) + +#define SFF_8636_RX_APP_SELECT_4_OFFSET 0x58 +#define SFF_8636_RX_APP_SELECT_3_OFFSET 0x59 +#define SFF_8636_RX_APP_SELECT_2_OFFSET 0x5A +#define SFF_8636_RX_APP_SELECT_1_OFFSET 0x5B + +#define SFF_8636_PWR_MODE_OFFSET 0x5D +#define SFF_8636_HIGH_PWR_ENABLE (1 << 2) +#define SFF_8636_LOW_PWR_MODE (1 << 1) +#define SFF_8636_PWR_OVERRIDE (1 << 0) + +#define SFF_8636_TX_APP_SELECT_4_OFFSET 0x5E +#define SFF_8636_TX_APP_SELECT_3_OFFSET 0x5F +#define SFF_8636_TX_APP_SELECT_2_OFFSET 0x60 +#define SFF_8636_TX_APP_SELECT_1_OFFSET 0x61 + +#define SFF_8636_LOS_MASK_OFFSET 0x64 +#define SFF_8636_TX_LOS_4_MASK (1 << 7) +#define SFF_8636_TX_LOS_3_MASK (1 << 6) +#define SFF_8636_TX_LOS_2_MASK (1 << 5) +#define SFF_8636_TX_LOS_1_MASK (1 << 4) +#define SFF_8636_RX_LOS_4_MASK (1 << 3) +#define SFF_8636_RX_LOS_3_MASK (1 << 2) +#define SFF_8636_RX_LOS_2_MASK (1 << 1) +#define SFF_8636_RX_LOS_1_MASK (1 << 0) + +#define SFF_8636_FAULT_MASK_OFFSET 0x65 +#define SFF_8636_TX_FAULT_1_MASK (1 << 3) +#define SFF_8636_TX_FAULT_2_MASK (1 << 2) +#define SFF_8636_TX_FAULT_3_MASK (1 << 1) +#define SFF_8636_TX_FAULT_4_MASK (1 << 0) + +#define SFF_8636_TEMP_MASK_OFFSET 0x67 +#define SFF_8636_TEMP_HALARM_MASK (1 << 7) +#define SFF_8636_TEMP_LALARM_MASK (1 << 6) +#define SFF_8636_TEMP_HWARN_MASK (1 << 5) +#define SFF_8636_TEMP_LWARN_MASK (1 << 4) + +#define SFF_8636_VCC_MASK_OFFSET 0x68 +#define SFF_8636_VCC_HALARM_MASK (1 << 7) +#define SFF_8636_VCC_LALARM_MASK (1 << 6) +#define SFF_8636_VCC_HWARN_MASK (1 << 5) +#define SFF_8636_VCC_LWARN_MASK (1 << 4) + +/*------------------------------------------------------------------------------ + * + * Upper Memory Page 00h + * Serial ID - Base ID, Extended ID and Vendor Specific ID fields + * + */ +/* Identifier - 128 */ +/* Identifier values same as Lower Memory Page 00h */ +#define SFF_8636_UPPER_PAGE_0_ID_OFFSET 0x80 + +/* Extended Identifier - 128 */ +#define SFF_8636_EXT_ID_OFFSET 0x81 +#define SFF_8636_EXT_ID_PWR_CLASS_MASK 0xC0 +#define SFF_8636_EXT_ID_PWR_CLASS_1 (0 << 6) +#define SFF_8636_EXT_ID_PWR_CLASS_2 (1 << 6) +#define SFF_8636_EXT_ID_PWR_CLASS_3 (2 << 6) +#define SFF_8636_EXT_ID_PWR_CLASS_4 (3 << 6) +#define SFF_8636_EXT_ID_CLIE_MASK 0x10 +#define SFF_8636_EXT_ID_CLIEI_CODE_PRESENT (1 << 4) +#define SFF_8636_EXT_ID_CDR_TX_MASK 0x08 +#define SFF_8636_EXT_ID_CDR_TX_PRESENT (1 << 3) +#define SFF_8636_EXT_ID_CDR_RX_MASK 0x04 +#define SFF_8636_EXT_ID_CDR_RX_PRESENT (1 << 2) +#define SFF_8636_EXT_ID_EPWR_CLASS_MASK 0x03 +#define SFF_8636_EXT_ID_PWR_CLASS_LEGACY 0 +#define SFF_8636_EXT_ID_PWR_CLASS_5 1 +#define SFF_8636_EXT_ID_PWR_CLASS_6 2 +#define SFF_8636_EXT_ID_PWR_CLASS_7 3 + +/* Connector Values offset - 130 */ +/* Values are defined under SFF_8024_CTOR */ +#define SFF_8636_CTOR_OFFSET 0x82 +#define SFF_8636_CTOR_UNKNOWN 0x00 +#define SFF_8636_CTOR_SC 0x01 +#define SFF_8636_CTOR_FC_STYLE_1 0x02 +#define SFF_8636_CTOR_FC_STYLE_2 0x03 +#define SFF_8636_CTOR_BNC_TNC 0x04 +#define SFF_8636_CTOR_FC_COAX 0x05 +#define SFF_8636_CTOR_FIBER_JACK 0x06 +#define SFF_8636_CTOR_LC 0x07 +#define SFF_8636_CTOR_MT_RJ 0x08 +#define SFF_8636_CTOR_MU 0x09 +#define SFF_8636_CTOR_SG 0x0A +#define SFF_8636_CTOR_OPT_PT 0x0B +#define SFF_8636_CTOR_MPO 0x0C +/* 0D-1Fh --- Reserved */ +#define SFF_8636_CTOR_HSDC_II 0x20 +#define SFF_8636_CTOR_COPPER_PT 0x21 +#define SFF_8636_CTOR_RJ45 0x22 +#define SFF_8636_CTOR_NO_SEPARABLE 0x23 +#define SFF_8636_CTOR_MXC_2X16 0x24 + +/* Specification Compliance - 131-138 */ +/* Ethernet Compliance Codes - 131 */ +#define SFF_8636_ETHERNET_COMP_OFFSET 0x83 +#define SFF_8636_ETHERNET_RSRVD (1 << 7) +#define SFF_8636_ETHERNET_10G_LRM (1 << 6) +#define SFF_8636_ETHERNET_10G_LR (1 << 5) +#define SFF_8636_ETHERNET_10G_SR (1 << 4) +#define SFF_8636_ETHERNET_40G_CR4 (1 << 3) +#define SFF_8636_ETHERNET_40G_SR4 (1 << 2) +#define SFF_8636_ETHERNET_40G_LR4 (1 << 1) +#define SFF_8636_ETHERNET_40G_ACTIVE (1 << 0) + +/* SONET Compliance Codes - 132 */ +#define SFF_8636_SONET_COMP_OFFSET 0x84 +#define SFF_8636_SONET_40G_OTN (1 << 3) +#define SFF_8636_SONET_OC48_LR (1 << 2) +#define SFF_8636_SONET_OC48_IR (1 << 1) +#define SFF_8636_SONET_OC48_SR (1 << 0) + +/* SAS/SATA Complaince Codes - 133 */ +#define SFF_8636_SAS_COMP_OFFSET 0x85 +#define SFF_8636_SAS_12G (1 << 6) +#define SFF_8636_SAS_6G (1 << 5) +#define SFF_8636_SAS_3G (1 << 4) + +/* Gigabit Ethernet Compliance Codes - 134 */ +#define SFF_8636_GIGE_COMP_OFFSET 0x86 +#define SFF_8636_GIGE_1000_BASE_T (1 << 3) +#define SFF_8636_GIGE_1000_BASE_CX (1 << 2) +#define SFF_8636_GIGE_1000_BASE_LX (1 << 1) +#define SFF_8636_GIGE_1000_BASE_SX (1 << 0) + +/* Fibre Channel Link length/Transmitter Tech. - 135,136 */ +#define SFF_8636_FC_LEN_OFFSET 0x87 +#define SFF_8636_FC_LEN_VERY_LONG (1 << 7) +#define SFF_8636_FC_LEN_SHORT (1 << 6) +#define SFF_8636_FC_LEN_INT (1 << 5) +#define SFF_8636_FC_LEN_LONG (1 << 4) +#define SFF_8636_FC_LEN_MED (1 << 3) +#define SFF_8636_FC_TECH_LONG_LC (1 << 1) +#define SFF_8636_FC_TECH_ELEC_INTER (1 << 0) + +#define SFF_8636_FC_TECH_OFFSET 0x88 +#define SFF_8636_FC_TECH_ELEC_INTRA (1 << 7) +#define SFF_8636_FC_TECH_SHORT_WO_OFC (1 << 6) +#define SFF_8636_FC_TECH_SHORT_W_OFC (1 << 5) +#define SFF_8636_FC_TECH_LONG_LL (1 << 4) + +/* Fibre Channel Transmitter Media - 137 */ +#define SFF_8636_FC_TRANS_MEDIA_OFFSET 0x89 +/* Twin Axial Pair */ +#define SFF_8636_FC_TRANS_MEDIA_TW (1 << 7) +/* Shielded Twisted Pair */ +#define SFF_8636_FC_TRANS_MEDIA_TP (1 << 6) +/* Miniature Coax */ +#define SFF_8636_FC_TRANS_MEDIA_MI (1 << 5) +/* Video Coax */ +#define SFF_8636_FC_TRANS_MEDIA_TV (1 << 4) +/* Multi-mode 62.5m */ +#define SFF_8636_FC_TRANS_MEDIA_M6 (1 << 3) +/* Multi-mode 50m */ +#define SFF_8636_FC_TRANS_MEDIA_M5 (1 << 2) +/* Multi-mode 50um */ +#define SFF_8636_FC_TRANS_MEDIA_OM3 (1 << 1) +/* Single Mode */ +#define SFF_8636_FC_TRANS_MEDIA_SM (1 << 0) + +/* Fibre Channel Speed - 138 */ +#define SFF_8636_FC_SPEED_OFFSET 0x8A +#define SFF_8636_FC_SPEED_1200_MBPS (1 << 7) +#define SFF_8636_FC_SPEED_800_MBPS (1 << 6) +#define SFF_8636_FC_SPEED_1600_MBPS (1 << 5) +#define SFF_8636_FC_SPEED_400_MBPS (1 << 4) +#define SFF_8636_FC_SPEED_200_MBPS (1 << 2) +#define SFF_8636_FC_SPEED_100_MBPS (1 << 0) + +/* Encoding - 139 */ +/* Values are defined under SFF_8024_ENCODING */ +#define SFF_8636_ENCODING_OFFSET 0x8B +#define SFF_8636_ENCODING_MANCHESTER 0x06 +#define SFF_8636_ENCODING_64B66B 0x05 +#define SFF_8636_ENCODING_SONET 0x04 +#define SFF_8636_ENCODING_NRZ 0x03 +#define SFF_8636_ENCODING_4B5B 0x02 +#define SFF_8636_ENCODING_8B10B 0x01 +#define SFF_8636_ENCODING_UNSPEC 0x00 + +/* BR, Nominal - 140 */ +#define SFF_8636_BR_NOMINAL_OFFSET 0x8C + +/* Extended RateSelect - 141 */ +#define SFF_8636_EXT_RS_OFFSET 0x8D +#define SFF_8636_EXT_RS_V1 (1 << 0) + +/* Length (Standard SM Fiber)-km - 142 */ +#define SFF_8636_SM_LEN_OFFSET 0x8E + +/* Length (OM3)-Unit 2m - 143 */ +#define SFF_8636_OM3_LEN_OFFSET 0x8F + +/* Length (OM2)-Unit 1m - 144 */ +#define SFF_8636_OM2_LEN_OFFSET 0x90 + +/* Length (OM1)-Unit 1m - 145 */ +#define SFF_8636_OM1_LEN_OFFSET 0x91 + +/* Cable Assembly Length -Unit 1m - 146 */ +#define SFF_8636_CBL_LEN_OFFSET 0x92 + +/* Device Technology - 147 */ +#define SFF_8636_DEVICE_TECH_OFFSET 0x93 +/* Transmitter Technology */ +#define SFF_8636_TRANS_TECH_MASK 0xF0 +/* Copper cable, linear active equalizers */ +#define SFF_8636_TRANS_COPPER_LNR_EQUAL (15 << 4) +/* Copper cable, near end limiting active equalizers */ +#define SFF_8636_TRANS_COPPER_NEAR_EQUAL (14 << 4) +/* Copper cable, far end limiting active equalizers */ +#define SFF_8636_TRANS_COPPER_FAR_EQUAL (13 << 4) +/* Copper cable, near & far end limiting active equalizers */ +#define SFF_8636_TRANS_COPPER_LNR_FAR_EQUAL (12 << 4) +/* Copper cable, passive equalized */ +#define SFF_8636_TRANS_COPPER_PAS_EQUAL (11 << 4) +/* Copper cable, unequalized */ +#define SFF_8636_TRANS_COPPER_PAS_UNEQUAL (10 << 4) +/* 1490 nm DFB */ +#define SFF_8636_TRANS_1490_DFB (9 << 4) +/* Others */ +#define SFF_8636_TRANS_OTHERS (8 << 4) +/* 1550 nm EML */ +#define SFF_8636_TRANS_1550_EML (7 << 4) +/* 1310 nm EML */ +#define SFF_8636_TRANS_1310_EML (6 << 4) +/* 1550 nm DFB */ +#define SFF_8636_TRANS_1550_DFB (5 << 4) +/* 1310 nm DFB */ +#define SFF_8636_TRANS_1310_DFB (4 << 4) +/* 1310 nm FP */ +#define SFF_8636_TRANS_1310_FP (3 << 4) +/* 1550 nm VCSEL */ +#define SFF_8636_TRANS_1550_VCSEL (2 << 4) +/* 1310 nm VCSEL */ +#define SFF_8636_TRANS_1310_VCSEL (1 << 4) +/* 850 nm VCSEL */ +#define SFF_8636_TRANS_850_VCSEL (0 << 4) + + /* Active/No wavelength control */ +#define SFF_8636_DEV_TECH_ACTIVE_WAVE_LEN (1 << 3) +/* Cooled transmitter */ +#define SFF_8636_DEV_TECH_COOL_TRANS (1 << 2) +/* APD/Pin Detector */ +#define SFF_8636_DEV_TECH_APD_DETECTOR (1 << 1) +/* Transmitter tunable */ +#define SFF_8636_DEV_TECH_TUNABLE (1 << 0) + +/* Vendor Name - 148-163 */ +#define SFF_8636_VENDOR_NAME_START_OFFSET 0x94 +#define SFF_8636_VENDOR_NAME_END_OFFSET 0xA3 + +/* Extended Module Codes - 164 */ +#define SFF_8636_EXT_MOD_CODE_OFFSET 0xA4 +#define SFF_8636_EXT_MOD_INFINIBAND_EDR (1 << 4) +#define SFF_8636_EXT_MOD_INFINIBAND_FDR (1 << 3) +#define SFF_8636_EXT_MOD_INFINIBAND_QDR (1 << 2) +#define SFF_8636_EXT_MOD_INFINIBAND_DDR (1 << 1) +#define SFF_8636_EXT_MOD_INFINIBAND_SDR (1 << 0) + +/* Vendor OUI - 165-167 */ +#define SFF_8636_VENDOR_OUI_OFFSET 0xA5 +#define SFF_8636_VENDOR_OUI_LEN 3 + +/* Vendor OUI - 165-167 */ +#define SFF_8636_VENDOR_PN_START_OFFSET 0xA8 +#define SFF_8636_VENDOR_PN_END_OFFSET 0xB7 + +/* Vendor Revision - 184-185 */ +#define SFF_8636_VENDOR_REV_START_OFFSET 0xB8 +#define SFF_8636_VENDOR_REV_END_OFFSET 0xB9 + +/* Wavelength - 186-187 */ +#define SFF_8636_WAVELEN_HIGH_BYTE_OFFSET 0xBA +#define SFF_8636_WAVELEN_LOW_BYTE_OFFSET 0xBB + +/* Wavelength Tolerance- 188-189 */ +#define SFF_8636_WAVE_TOL_HIGH_BYTE_OFFSET 0xBC +#define SFF_8636_WAVE_TOL_LOW_BYTE_OFFSET 0xBD + +/* Max case temp - Other than 70 C - 190 */ +#define SFF_8636_MAXCASE_TEMP_OFFSET 0xBE + +/* CC_BASE - 191 */ +#define SFF_8636_CC_BASE_OFFSET 0xBF + +/* Option Values - 192-195 */ +#define SFF_8636_OPTION_1_OFFSET 0xC0 +#define SFF_8636_ETHERNET_UNSPECIFIED 0x00 +#define SFF_8636_ETHERNET_100G_AOC 0x01 +#define SFF_8636_ETHERNET_100G_SR4 0x02 +#define SFF_8636_ETHERNET_100G_LR4 0x03 +#define SFF_8636_ETHERNET_100G_ER4 0x04 +#define SFF_8636_ETHERNET_100G_SR10 0x05 +#define SFF_8636_ETHERNET_100G_CWDM4_FEC 0x06 +#define SFF_8636_ETHERNET_100G_PSM4 0x07 +#define SFF_8636_ETHERNET_100G_ACC 0x08 +#define SFF_8636_ETHERNET_100G_CWDM4_NO_FEC 0x09 +#define SFF_8636_ETHERNET_100G_RSVD1 0x0A +#define SFF_8636_ETHERNET_100G_CR4 0x0B +#define SFF_8636_ETHERNET_25G_CR_CA_S 0x0C +#define SFF_8636_ETHERNET_25G_CR_CA_N 0x0D +#define SFF_8636_ETHERNET_40G_ER4 0x10 +#define SFF_8636_ETHERNET_4X10_SR 0x11 +#define SFF_8636_ETHERNET_40G_PSM4 0x12 +#define SFF_8636_ETHERNET_G959_P1I1_2D1 0x13 +#define SFF_8636_ETHERNET_G959_P1S1_2D2 0x14 +#define SFF_8636_ETHERNET_G959_P1L1_2D2 0x15 +#define SFF_8636_ETHERNET_10GT_SFI 0x16 +#define SFF_8636_ETHERNET_100G_CLR4 0x17 +#define SFF_8636_ETHERNET_100G_AOC2 0x18 +#define SFF_8636_ETHERNET_100G_ACC2 0x19 + +#define SFF_8636_OPTION_2_OFFSET 0xC1 +/* Rx output amplitude */ +#define SFF_8636_O2_RX_OUTPUT_AMP (1 << 0) +#define SFF_8636_OPTION_3_OFFSET 0xC2 +/* Rx Squelch Disable */ +#define SFF_8636_O3_RX_SQL_DSBL (1 << 3) +/* Rx Output Disable capable */ +#define SFF_8636_O3_RX_OUTPUT_DSBL (1 << 2) +/* Tx Squelch Disable */ +#define SFF_8636_O3_TX_SQL_DSBL (1 << 1) +/* Tx Squelch Impl */ +#define SFF_8636_O3_TX_SQL_IMPL (1 << 0) +#define SFF_8636_OPTION_4_OFFSET 0xC3 +/* Memory Page 02 present */ +#define SFF_8636_O4_PAGE_02_PRESENT (1 << 7) +/* Memory Page 01 present */ +#define SFF_8636_O4_PAGE_01_PRESENT (1 << 6) +/* Rate Select implemented */ +#define SFF_8636_O4_RATE_SELECT (1 << 5) +/* Tx_DISABLE implemented */ +#define SFF_8636_O4_TX_DISABLE (1 << 4) +/* Tx_FAULT implemented */ +#define SFF_8636_O4_TX_FAULT (1 << 3) +/* Tx Squelch implemented */ +#define SFF_8636_O4_TX_SQUELCH (1 << 2) +/* Tx Loss of Signal */ +#define SFF_8636_O4_TX_LOS (1 << 1) + +/* Vendor SN - 196-211 */ +#define SFF_8636_VENDOR_SN_START_OFFSET 0xC4 +#define SFF_8636_VENDOR_SN_END_OFFSET 0xD3 + +/* Vendor Date - 212-219 */ +#define SFF_8636_DATE_YEAR_OFFSET 0xD4 +#define SFF_8636_DATE_YEAR_LEN 2 +#define SFF_8636_DATE_MONTH_OFFSET 0xD6 +#define SFF_8636_DATE_MONTH_LEN 2 +#define SFF_8636_DATE_DAY_OFFSET 0xD8 +#define SFF_8636_DATE_DAY_LEN 2 +#define SFF_8636_DATE_VENDOR_LOT_OFFSET 0xDA +#define SFF_8636_DATE_VENDOR_LOT_LEN 2 + +/* Diagnostic Monitoring Type - 220 */ +#define SFF_8636_DIAG_TYPE_OFFSET 0xDC +#define SFF_8636_RX_PWR_TYPE_MASK 0x8 +#define SFF_8636_RX_PWR_TYPE_AVG_PWR (1 << 3) +#define SFF_8636_RX_PWR_TYPE_OMA (0 << 3) +#define SFF_8636_TX_PWR_TYPE_MASK 0x4 +#define SFF_8636_TX_PWR_TYPE_AVG_PWR (1 << 2) + +/* Enhanced Options - 221 */ +#define SFF_8636_ENH_OPTIONS_OFFSET 0xDD +#define SFF_8636_RATE_SELECT_EXT_SUPPORT (1 << 3) +#define SFF_8636_RATE_SELECT_APP_TABLE_SUPPORT (1 << 2) + +/* Check code - 223 */ +#define SFF_8636_CC_EXT_OFFSET 0xDF +#define SFF_8636_CC_EXT_LEN 1 + +/*------------------------------------------------------------------------------ + * + * Upper Memory Page 03h + * Contains module thresholds, channel thresholds and masks, + * and optional channel controls + * + * Offset - Page Num(3) * PageSize(0x80) + Page offset + */ + +/* Module Thresholds (48 Bytes) 128-175 */ +/* MSB at low address, LSB at high address */ +#define SFF_8636_TEMP_HALRM 0x200 +#define SFF_8636_TEMP_LALRM 0x202 +#define SFF_8636_TEMP_HWARN 0x204 +#define SFF_8636_TEMP_LWARN 0x206 + +#define SFF_8636_VCC_HALRM 0x210 +#define SFF_8636_VCC_LALRM 0x212 +#define SFF_8636_VCC_HWARN 0x214 +#define SFF_8636_VCC_LWARN 0x216 + +#define SFF_8636_RX_PWR_HALRM 0x230 +#define SFF_8636_RX_PWR_LALRM 0x232 +#define SFF_8636_RX_PWR_HWARN 0x234 +#define SFF_8636_RX_PWR_LWARN 0x236 + +#define SFF_8636_TX_BIAS_HALRM 0x238 +#define SFF_8636_TX_BIAS_LALRM 0x23A +#define SFF_8636_TX_BIAS_HWARN 0x23C +#define SFF_8636_TX_BIAS_LWARN 0x23E + +#define SFF_8636_TX_PWR_HALRM 0x240 +#define SFF_8636_TX_PWR_LALRM 0x242 +#define SFF_8636_TX_PWR_HWARN 0x244 +#define SFF_8636_TX_PWR_LWARN 0x246 + +#define ETH_MODULE_SFF_8636_MAX_LEN 640 +#define ETH_MODULE_SFF_8436_MAX_LEN 640 + +const uint8_t rx_power_offset[MAX_CHANNEL_NUM] = { + SFF_8636_RX_PWR_1_OFFSET, + SFF_8636_RX_PWR_2_OFFSET, + SFF_8636_RX_PWR_3_OFFSET, + SFF_8636_RX_PWR_4_OFFSET, +}; +const uint8_t tx_power_offset[MAX_CHANNEL_NUM] = { + SFF_8636_TX_PWR_1_OFFSET, + SFF_8636_TX_PWR_2_OFFSET, + SFF_8636_TX_PWR_3_OFFSET, + SFF_8636_TX_PWR_4_OFFSET, +}; +const uint8_t tx_bias_offset[MAX_CHANNEL_NUM] = { + SFF_8636_TX_BIAS_1_OFFSET, + SFF_8636_TX_BIAS_2_OFFSET, + SFF_8636_TX_BIAS_3_OFFSET, + SFF_8636_TX_BIAS_4_OFFSET, +}; + +#endif /* _SFF_8636_H_ */ -- 2.25.1