From: Tomasz Duszynski <tduszynski@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Jakub Palider <jpalider@marvell.com>,
"Tomasz Duszynski" <tduszynski@marvell.com>
Cc: <thomas@monjalon.net>, <jerinj@marvell.com>
Subject: [PATCH 10/10] common/cnxk: support switching CPRI/ETH back and forth
Date: Sat, 4 Jun 2022 18:26:51 +0200 [thread overview]
Message-ID: <20220604162651.3503338-11-tduszynski@marvell.com> (raw)
In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com>
Add support for toggling modes between ETH and CPRI on
newer MACs (RPM).
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
drivers/common/cnxk/roc_bphy_cgx.h | 17 ++++++++++++++++-
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 14 ++++++++++++--
drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 27 +++++++++++++++++++++++++--
3 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 4ce1316513..2b9a23f5b1 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -86,8 +86,20 @@ enum roc_bphy_cgx_eth_link_mode {
__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
};
+/* Supported CPRI modes */
+enum roc_bphy_cgx_eth_mode_cpri {
+ ROC_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT,
+ ROC_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT,
+ ROC_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT,
+ ROC_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT,
+ ROC_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT,
+ ROC_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT,
+ ROC_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT,
+};
+
enum roc_bphy_cgx_mode_group {
ROC_BPHY_CGX_MODE_GROUP_ETH,
+ ROC_BPHY_CGX_MODE_GROUP_CPRI = 2,
};
struct roc_bphy_cgx_link_mode {
@@ -97,7 +109,10 @@ struct roc_bphy_cgx_link_mode {
unsigned int portm_idx;
enum roc_bphy_cgx_mode_group mode_group_idx;
enum roc_bphy_cgx_eth_link_speed speed;
- enum roc_bphy_cgx_eth_link_mode mode;
+ union {
+ enum roc_bphy_cgx_eth_link_mode mode;
+ enum roc_bphy_cgx_eth_mode_cpri mode_cpri;
+ };
};
struct roc_bphy_cgx_link_info {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index f839a70f04..26def43564 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -118,8 +118,18 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
(enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx;
rlink_mode.speed =
(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
- rlink_mode.mode =
- (enum roc_bphy_cgx_eth_link_mode)link_mode->mode;
+ switch (link_mode->mode_group_idx) {
+ case CNXK_BPHY_CGX_MODE_GROUP_ETH:
+ rlink_mode.mode =
+ (enum roc_bphy_cgx_eth_link_mode)
+ link_mode->mode;
+ break;
+ case CNXK_BPHY_CGX_MODE_GROUP_CPRI:
+ rlink_mode.mode_cpri =
+ (enum roc_bphy_cgx_eth_mode_cpri)
+ link_mode->mode_cpri;
+ break;
+ }
ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);
break;
case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 7f326e3643..f9949fa313 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -168,9 +168,28 @@ enum cnxk_bphy_cgx_eth_link_mode {
__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
};
+enum cnxk_bphy_cgx_eth_mode_cpri {
+ /** 2.4G Lane Rate */
+ CNXK_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT,
+ /** 3.1G Lane Rate */
+ CNXK_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT,
+ /** 4.9G Lane Rate */
+ CNXK_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT,
+ /** 6.1G Lane Rate */
+ CNXK_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT,
+ /** 9.8G Lane Rate */
+ CNXK_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT,
+ /** 10.1G Lane Rate */
+ CNXK_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT,
+ /** 24.3G Lane Rate */
+ CNXK_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT,
+};
+
enum cnxk_bphy_cgx_mode_group {
/** ETH group */
CNXK_BPHY_CGX_MODE_GROUP_ETH,
+ /** CPRI group */
+ CNXK_BPHY_CGX_MODE_GROUP_CPRI = 2,
};
struct cnxk_bphy_cgx_msg_link_mode {
@@ -186,8 +205,12 @@ struct cnxk_bphy_cgx_msg_link_mode {
enum cnxk_bphy_cgx_mode_group mode_group_idx;
/** Link speed */
enum cnxk_bphy_cgx_eth_link_speed speed;
- /** Link mode */
- enum cnxk_bphy_cgx_eth_link_mode mode;
+ union {
+ /** Link mode */
+ enum cnxk_bphy_cgx_eth_link_mode mode;
+ /** CPRI mode */
+ enum cnxk_bphy_cgx_eth_mode_cpri mode_cpri;
+ };
};
struct cnxk_bphy_cgx_msg_link_info {
--
2.25.1
next prev parent reply other threads:[~2022-06-04 16:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-04 16:26 [PATCH 00/10] Sync BPHY changes Tomasz Duszynski
2022-06-04 16:26 ` [PATCH 01/10] common/cnxk: update register access for CNF10xxN Tomasz Duszynski
2022-06-04 16:26 ` [PATCH 02/10] common/cnxk: use wider mask to extract RPM ID Tomasz Duszynski
2022-06-04 16:26 ` [PATCH 03/10] raw/cnxk_bphy: add doxygen comments Tomasz Duszynski
2022-06-04 16:26 ` [PATCH 04/10] common/cnxk: don't switch affinity back and forth Tomasz Duszynski
2022-06-04 16:26 ` [PATCH 05/10] raw/cnxk_bphy: support switching from eCPRI to CPRI Tomasz Duszynski
2022-06-07 9:09 ` Ray Kinsella
2022-06-04 16:26 ` [PATCH 06/10] raw/cnxk_bphy: support enabling TX for CPRI SERDES Tomasz Duszynski
2022-06-07 9:09 ` Ray Kinsella
2022-06-04 16:26 ` [PATCH 07/10] raw/cnxk_bphy: support changing CPRI misc settings Tomasz Duszynski
2022-06-07 9:11 ` Ray Kinsella
2022-06-04 16:26 ` [PATCH 08/10] common/cnxk: remove unused constants Tomasz Duszynski
2022-06-04 16:26 ` [PATCH 09/10] common/cnxk: sync eth mode change command with firmware Tomasz Duszynski
2022-06-04 16:26 ` Tomasz Duszynski [this message]
2022-06-14 7:09 ` [PATCH 00/10] Sync BPHY changes Tomasz Duszynski
2022-06-22 7:04 ` Thomas Monjalon
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