[PATCH 06/10] raw/cnxk_bphy: support enabling TX for CPRI SERDES

[Tomasz Duszynski <tduszynski@marvell.com>]

Add support for enabling or disablig TX for SERDES
configured in CPRI mode.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst        | 10 +++++++
 drivers/common/cnxk/roc_bphy_cgx.c      | 31 +++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  8 ++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  6 +++++
 drivers/common/cnxk/version.map         |  1 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c   | 11 ++++++++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h    | 36 +++++++++++++++++++++++++
 7 files changed, 103 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 7f55e9eac6..50ee9bdaa6 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -111,6 +111,16 @@ Prior to sending actual message payload i.e
 ``struct cnxk_bphy_cgx_msg_cpri_mode_change`` needs to be filled with relevant
 information.
 
+Enable TX for CPRI SERDES
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used to enable TX for SERDES configured in CPRI mode.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL``.
+Prior to sending actual message payload i.e
+``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant
+information.
+
 BPHY PMD
 --------
 
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 223bd313fa..ee0198924e 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -488,3 +488,34 @@ roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
+
+int
+roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx,
+				  unsigned int lmac,
+				  struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode)
+{
+	uint64_t scr1, scr0;
+
+	if (!(roc_model_is_cnf95xxn_a0() ||
+	      roc_model_is_cnf95xxn_a1() ||
+	      roc_model_is_cnf95xxn_b0()))
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	if (!mode)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_TX_CONTROL) |
+	       FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX,
+			  mode->gserc_idx) |
+	       FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX,
+			  mode->lane_idx) |
+	       FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE, mode->enable);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 59adddd420..b8023cce88 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -100,6 +100,12 @@ struct roc_bphy_cgx_cpri_mode_change {
 	bool disable_dfe;
 };
 
+struct roc_bphy_cgx_cpri_mode_tx_ctrl {
+	int gserc_idx;
+	int lane_idx;
+	bool enable;
+};
+
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
@@ -130,5 +136,7 @@ __roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsig
 					     enum roc_bphy_cgx_eth_link_fec *fec);
 __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 					    struct roc_bphy_cgx_cpri_mode_change *mode);
+__roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+						struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode);
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index cdd94989c8..96db34f6a1 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -70,6 +70,7 @@ enum eth_cmd_id {
 	ETH_CMD_SET_FEC = 19,
 	ETH_CMD_SET_PTP_MODE = 34,
 	ETH_CMD_CPRI_MODE_CHANGE = 35,
+	ETH_CMD_CPRI_TX_CONTROL = 36,
 };
 
 /* event types - cause of interrupt */
@@ -141,6 +142,11 @@ enum eth_cmd_own {
 #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ BIT_ULL(32)
 #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE BIT_ULL(33)
 
+/* struct cpri_mode_tx_ctrl_args */
+#define SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX GENMASK_ULL(11, 8)
+#define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX  GENMASK_ULL(15, 12)
+#define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE    BIT_ULL(16)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 720cad61ea..a6183799a9 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -29,6 +29,7 @@ INTERNAL {
 	roc_ae_fpm_put;
 	roc_aes_xcbc_key_derive;
 	roc_bphy_cgx_cpri_mode_change;
+	roc_bphy_cgx_cpri_mode_tx_control;
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
 	roc_bphy_cgx_fec_set;
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 803b245c78..bdc65a7f2a 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -58,10 +58,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
 	struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];
 	struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode;
 	struct cnxk_bphy_cgx_msg_set_link_state *link_state;
+	struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl;
 	struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
 	struct cnxk_bphy_cgx_msg_link_mode *link_mode;
 	struct cnxk_bphy_cgx_msg_link_info *link_info;
 	struct roc_bphy_cgx_cpri_mode_change rcpri_mode;
+	struct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl;
 	struct roc_bphy_cgx_link_info rlink_info;
 	struct roc_bphy_cgx_link_mode rlink_mode;
 	enum roc_bphy_cgx_eth_link_fec *fec;
@@ -148,6 +150,15 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
 		ret = roc_bphy_cgx_cpri_mode_change(cgx->rcgx, lmac,
 						    &rcpri_mode);
 		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL:
+		tx_ctrl = msg->data;
+		memset(&rtx_ctrl, 0, sizeof(rtx_ctrl));
+		rtx_ctrl.gserc_idx = tx_ctrl->gserc_idx;
+		rtx_ctrl.lane_idx = tx_ctrl->lane_idx;
+		rtx_ctrl.enable = tx_ctrl->enable;
+		ret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac,
+							&rtx_ctrl);
+		break;
 	default:
 		return -EINVAL;
 	}
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 36b75aa385..79bb2233bc 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -52,6 +52,8 @@ enum cnxk_bphy_cgx_msg_type {
 	CNXK_BPHY_CGX_MSG_TYPE_SET_FEC,
 	/** Type used to switch from eCPRI to CPRI */
 	CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE,
+	/** Type used to enable TX for CPRI SERDES */
+	CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL,
 };
 
 /** Available link speeds */
@@ -186,6 +188,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_change {
 	bool disable_dfe;
 };
 
+struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl {
+	/** SERDES index (0 - 4) */
+	int gserc_idx;
+	/** Lane index (0 - 1) */
+	int lane_idx;
+	/** Disable or enable SERDES */
+	bool enable;
+};
+
 struct cnxk_bphy_cgx_msg {
 	/** Message type */
 	enum cnxk_bphy_cgx_msg_type type;
@@ -734,6 +745,31 @@ rte_pmd_bphy_cgx_cpri_mode_change(uint16_t dev_id, uint16_t lmac,
 	return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
 }
 
+/**
+ * Enable TX for SERDES configured in CPRI mode
+ *
+ * @param dev_id
+ *   The identifier of the device
+ * @param lmac
+ *   LMAC number for operation
+ * @param mode
+ *   CPRI TX control structure holding control data
+ *
+ * @return
+ *   Returns 0 on success, negative error code otherwise
+ */
+static __rte_always_inline int
+rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac,
+				 struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *mode)
+{
+	struct cnxk_bphy_cgx_msg msg = {
+		.type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL,
+		.data = mode,
+	};
+
+	return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
+}
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.25.1