From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C06E9A034C; Sat, 4 Jun 2022 18:29:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 631CA415D7; Sat, 4 Jun 2022 18:29:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5F3A8415D7 for ; Sat, 4 Jun 2022 18:29:33 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254GMx3o022379; Sat, 4 Jun 2022 09:27:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=zqHD4uf/nFhrewhNI0e/iMp2JzeHyf7rUoAAnn8rOYk=; b=AVmU4lUiAjDm5M3vOtmhnGThQ6Ri8jDHwa5UCcK/y6EYtN6r0YMAfkEX1GmI/r9XOCn7 qvc6JRPljVGT+qWQ6JMjLou6j2xJsRCBsJb3ZW0sougNiI4NMLFRwyKW+rzVs1NB81i3 0rSEF4P20LbJOPgXAytWMvSo2cf1qAgca150O03HSNMDqkWp+ZB9o+A2N/MmjTnpb8uf Va1owl7DYtU/ifzkVfIAml9HTLr+/bauO2PXR4oLzqD6w0tnzaJe/9c3TRZODbWvb2// Yu9oilQTgky2I/WIrm/tcwbYbiaN5JtpW4lbWsbuXOlf734+B3ILnvMwtPaE1RJq7I2F IA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dh8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:27:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 4 Jun 2022 09:27:28 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id D909C3F7097; Sat, 4 Jun 2022 09:27:25 -0700 (PDT) From: Tomasz Duszynski To: , Jakub Palider , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 06/10] raw/cnxk_bphy: support enabling TX for CPRI SERDES Date: Sat, 4 Jun 2022 18:26:47 +0200 Message-ID: <20220604162651.3503338-7-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: YRjzlJR8n7RwumgCkiF52kWToToe1Q5n X-Proofpoint-GUID: YRjzlJR8n7RwumgCkiF52kWToToe1Q5n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for enabling or disablig TX for SERDES configured in CPRI mode. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- doc/guides/rawdevs/cnxk_bphy.rst | 10 +++++++ drivers/common/cnxk/roc_bphy_cgx.c | 31 +++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 8 ++++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 6 +++++ drivers/common/cnxk/version.map | 1 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 11 ++++++++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 36 +++++++++++++++++++++++++ 7 files changed, 103 insertions(+) diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst index 7f55e9eac6..50ee9bdaa6 100644 --- a/doc/guides/rawdevs/cnxk_bphy.rst +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -111,6 +111,16 @@ Prior to sending actual message payload i.e ``struct cnxk_bphy_cgx_msg_cpri_mode_change`` needs to be filled with relevant information. +Enable TX for CPRI SERDES +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Message is used to enable TX for SERDES configured in CPRI mode. + +Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL``. +Prior to sending actual message payload i.e +``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant +information. + BPHY PMD -------- diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 223bd313fa..ee0198924e 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -488,3 +488,34 @@ roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); } + +int +roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode) +{ + uint64_t scr1, scr0; + + if (!(roc_model_is_cnf95xxn_a0() || + roc_model_is_cnf95xxn_a1() || + roc_model_is_cnf95xxn_b0())) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -ENODEV; + + if (!mode) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_TX_CONTROL) | + FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX, + mode->gserc_idx) | + FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX, + mode->lane_idx) | + FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE, mode->enable); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 59adddd420..b8023cce88 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -100,6 +100,12 @@ struct roc_bphy_cgx_cpri_mode_change { bool disable_dfe; }; +struct roc_bphy_cgx_cpri_mode_tx_ctrl { + int gserc_idx; + int lane_idx; + bool enable; +}; + __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); @@ -130,5 +136,7 @@ __roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsig enum roc_bphy_cgx_eth_link_fec *fec); __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_cpri_mode_change *mode); +__roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode); #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index cdd94989c8..96db34f6a1 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -70,6 +70,7 @@ enum eth_cmd_id { ETH_CMD_SET_FEC = 19, ETH_CMD_SET_PTP_MODE = 34, ETH_CMD_CPRI_MODE_CHANGE = 35, + ETH_CMD_CPRI_TX_CONTROL = 36, }; /* event types - cause of interrupt */ @@ -141,6 +142,11 @@ enum eth_cmd_own { #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ BIT_ULL(32) #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE BIT_ULL(33) +/* struct cpri_mode_tx_ctrl_args */ +#define SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX GENMASK_ULL(11, 8) +#define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX GENMASK_ULL(15, 12) +#define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE BIT_ULL(16) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 720cad61ea..a6183799a9 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -29,6 +29,7 @@ INTERNAL { roc_ae_fpm_put; roc_aes_xcbc_key_derive; roc_bphy_cgx_cpri_mode_change; + roc_bphy_cgx_cpri_mode_tx_control; roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; roc_bphy_cgx_fec_set; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index 803b245c78..bdc65a7f2a 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -58,10 +58,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue]; struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode; struct cnxk_bphy_cgx_msg_set_link_state *link_state; + struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl; struct cnxk_bphy_cgx_msg *msg = buf->buf_addr; struct cnxk_bphy_cgx_msg_link_mode *link_mode; struct cnxk_bphy_cgx_msg_link_info *link_info; struct roc_bphy_cgx_cpri_mode_change rcpri_mode; + struct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl; struct roc_bphy_cgx_link_info rlink_info; struct roc_bphy_cgx_link_mode rlink_mode; enum roc_bphy_cgx_eth_link_fec *fec; @@ -148,6 +150,15 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, ret = roc_bphy_cgx_cpri_mode_change(cgx->rcgx, lmac, &rcpri_mode); break; + case CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL: + tx_ctrl = msg->data; + memset(&rtx_ctrl, 0, sizeof(rtx_ctrl)); + rtx_ctrl.gserc_idx = tx_ctrl->gserc_idx; + rtx_ctrl.lane_idx = tx_ctrl->lane_idx; + rtx_ctrl.enable = tx_ctrl->enable; + ret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac, + &rtx_ctrl); + break; default: return -EINVAL; } diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 36b75aa385..79bb2233bc 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -52,6 +52,8 @@ enum cnxk_bphy_cgx_msg_type { CNXK_BPHY_CGX_MSG_TYPE_SET_FEC, /** Type used to switch from eCPRI to CPRI */ CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, + /** Type used to enable TX for CPRI SERDES */ + CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, }; /** Available link speeds */ @@ -186,6 +188,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_change { bool disable_dfe; }; +struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl { + /** SERDES index (0 - 4) */ + int gserc_idx; + /** Lane index (0 - 1) */ + int lane_idx; + /** Disable or enable SERDES */ + bool enable; +}; + struct cnxk_bphy_cgx_msg { /** Message type */ enum cnxk_bphy_cgx_msg_type type; @@ -734,6 +745,31 @@ rte_pmd_bphy_cgx_cpri_mode_change(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Enable TX for SERDES configured in CPRI mode + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param mode + * CPRI TX control structure holding control data + * + * @return + * Returns 0 on success, negative error code otherwise + */ +static __rte_always_inline int +rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac, + struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *mode) +{ + struct cnxk_bphy_cgx_msg msg = { + .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, + .data = mode, + }; + + return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); +} + #ifdef __cplusplus } #endif -- 2.25.1