[PATCH 07/10] raw/cnxk_bphy: support changing CPRI misc settings

[Tomasz Duszynski <tduszynski@marvell.com>]

Add support for changing miscellaneous CPRI settings.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst        | 11 ++++++++
 drivers/common/cnxk/roc_bphy_cgx.c      | 30 +++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  8 ++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  6 +++++
 drivers/common/cnxk/version.map         |  1 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c   | 10 +++++++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h    | 36 +++++++++++++++++++++++++
 7 files changed, 102 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 50ee9bdaa6..2490912534 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -121,6 +121,17 @@ Prior to sending actual message payload i.e
 ``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant
 information.
 
+Change CPRI misc settings
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used to change misc CPRI settings, for example to reset RX state
+machine on CPRI SERDES.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC``.
+Prior to sending actual message payload i.e
+``struct cnxk_bphy_cgx_msg_cpri_mode_misc`` needs to be filled with relevant
+information.
+
 BPHY PMD
 --------
 
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index ee0198924e..4b62905164 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -519,3 +519,33 @@ roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx,
 
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
+
+int
+roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    struct roc_bphy_cgx_cpri_mode_misc *mode)
+{
+	uint64_t scr1, scr0;
+
+	if (!(roc_model_is_cnf95xxn_a0() ||
+	      roc_model_is_cnf95xxn_a1() ||
+	      roc_model_is_cnf95xxn_b0()))
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	if (!mode)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MISC) |
+	       FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX,
+			  mode->gserc_idx) |
+	       FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX,
+			  mode->lane_idx) |
+	       FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_FLAGS, mode->flags);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index b8023cce88..3b645eb130 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -106,6 +106,12 @@ struct roc_bphy_cgx_cpri_mode_tx_ctrl {
 	bool enable;
 };
 
+struct roc_bphy_cgx_cpri_mode_misc {
+	int gserc_idx;
+	int lane_idx;
+	int flags;
+};
+
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
@@ -138,5 +144,7 @@ __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsign
 					    struct roc_bphy_cgx_cpri_mode_change *mode);
 __roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 						struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode);
+__roc_api int roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+					  struct roc_bphy_cgx_cpri_mode_misc *mode);
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 96db34f6a1..a1a4239cbe 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -71,6 +71,7 @@ enum eth_cmd_id {
 	ETH_CMD_SET_PTP_MODE = 34,
 	ETH_CMD_CPRI_MODE_CHANGE = 35,
 	ETH_CMD_CPRI_TX_CONTROL = 36,
+	ETH_CMD_CPRI_MISC = 42,
 };
 
 /* event types - cause of interrupt */
@@ -147,6 +148,11 @@ enum eth_cmd_own {
 #define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX  GENMASK_ULL(15, 12)
 #define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE    BIT_ULL(16)
 
+/* struct cpri_mode_misc_args */
+#define SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX GENMASK_ULL(11, 8)
+#define SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX  GENMASK_ULL(15, 12)
+#define SCR1_CPRI_MODE_MISC_ARGS_FLAGS     GENMASK_ULL(17, 16)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index a6183799a9..d5fd1f41c2 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -29,6 +29,7 @@ INTERNAL {
 	roc_ae_fpm_put;
 	roc_aes_xcbc_key_derive;
 	roc_bphy_cgx_cpri_mode_change;
+	roc_bphy_cgx_cpri_mode_misc;
 	roc_bphy_cgx_cpri_mode_tx_control;
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index bdc65a7f2a..de1c372334 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -59,10 +59,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
 	struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode;
 	struct cnxk_bphy_cgx_msg_set_link_state *link_state;
 	struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl;
+	struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode_misc;
 	struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
 	struct cnxk_bphy_cgx_msg_link_mode *link_mode;
 	struct cnxk_bphy_cgx_msg_link_info *link_info;
 	struct roc_bphy_cgx_cpri_mode_change rcpri_mode;
+	struct roc_bphy_cgx_cpri_mode_misc rmode_misc;
 	struct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl;
 	struct roc_bphy_cgx_link_info rlink_info;
 	struct roc_bphy_cgx_link_mode rlink_mode;
@@ -159,6 +161,14 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
 		ret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac,
 							&rtx_ctrl);
 		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC:
+		mode_misc = msg->data;
+		memset(&rmode_misc, 0, sizeof(rmode_misc));
+		rmode_misc.gserc_idx = mode_misc->gserc_idx;
+		rmode_misc.lane_idx = mode_misc->lane_idx;
+		rmode_misc.flags = mode_misc->flags;
+		ret = roc_bphy_cgx_cpri_mode_misc(cgx->rcgx, lmac, &rmode_misc);
+		break;
 	default:
 		return -EINVAL;
 	}
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 79bb2233bc..86e58e4756 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -54,6 +54,8 @@ enum cnxk_bphy_cgx_msg_type {
 	CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE,
 	/** Type used to enable TX for CPRI SERDES */
 	CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL,
+	/** Type use to change misc CPRI SERDES settings */
+	CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC,
 };
 
 /** Available link speeds */
@@ -197,6 +199,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl {
 	bool enable;
 };
 
+struct cnxk_bphy_cgx_msg_cpri_mode_misc {
+	/** SERDES index (0 - 4) */
+	int gserc_idx;
+	/** Lane index (0 - 1) */
+	int lane_idx;
+	/** Misc flags (0 - RX Eq, 1 - RX state machine reset) */
+	int flags;
+};
+
 struct cnxk_bphy_cgx_msg {
 	/** Message type */
 	enum cnxk_bphy_cgx_msg_type type;
@@ -770,6 +781,31 @@ rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac,
 	return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
 }
 
+/**
+ * CPRI misc settings
+ *
+ * @param dev_id
+ *   The identifier of the device
+ * @param lmac
+ *   LMAC number for operation
+ * @param mode
+ *   CPRI settings holding misc control data
+ *
+ * @return
+ *   Returns 0 on success, negative error code otherwise
+ */
+static __rte_always_inline int
+rte_pmd_bphy_cgx_cpri_mode_misc(uint16_t dev_id, uint16_t lmac,
+				struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode)
+{
+	struct cnxk_bphy_cgx_msg msg = {
+		.type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC,
+		.data = mode,
+	};
+
+	return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
+}
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.25.1