From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 87575A0542; Mon, 6 Jun 2022 15:51:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 388B04067E; Mon, 6 Jun 2022 15:51:04 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 4217D40150 for ; Mon, 6 Jun 2022 15:51:02 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9BxieTe_J1imxwXAA--.64917S5; Mon, 06 Jun 2022 21:10:59 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v3 03/24] eal/loongarch: add cpu cycle operations for LoongArch Date: Mon, 6 Jun 2022 21:10:33 +0800 Message-Id: <20220606131054.2097526-4-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606131054.2097526-1-zhoumin@loongson.cn> References: <20220606131054.2097526-1-zhoumin@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: AQAAf9BxieTe_J1imxwXAA--.64917S5 X-Coremail-Antispam: 1UD129KBjvJXoWxGw1DXw47trWrXFWrXw1UJrb_yoW5ZrW8pr WUCFs3uw48Kr4xKrZ3X3s8WF1rJF4xCF9rGFyxAr40kr9rX34kua18KFW3AFyfXw4UuFyx XF4kWayY9FnrXw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds architecture specific cpu cycle operations for LoongArch. The RDTIME.D instruction is used to read constant frequency timer information including counter value. The CPUCFG instruction is used to dynamically identify which features of LoongArch are implemented in the running processor during the execution of the software. We can use this instruction to calculate the frequency used by the timer. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_cycles.h | 53 ++++++++++++++++++++++++++ lib/eal/loongarch/rte_cycles.c | 45 ++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_cycles.h create mode 100644 lib/eal/loongarch/rte_cycles.c diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h new file mode 100644 index 0000000000..1f8f957faf --- /dev/null +++ b/lib/eal/loongarch/include/rte_cycles.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_CYCLES_LOONGARCH_H_ +#define _RTE_CYCLES_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_cycles.h" + +static inline uint64_t +get_cycle_count(void) +{ + uint64_t count; + + __asm__ __volatile__ ( + "rdtime.d %[cycles], $zero\n" + : [cycles] "=r" (count) + :: + ); + return count; +} + +/** + * Read the time base register. + * + * @return + * The time base for this lcore. + */ +static inline uint64_t +rte_rdtsc(void) +{ + return get_cycle_count(); +} + +static inline uint64_t +rte_rdtsc_precise(void) +{ + rte_mb(); + return rte_rdtsc(); +} + +static inline uint64_t +rte_get_tsc_cycles(void) { return rte_rdtsc(); } + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CYCLES_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c new file mode 100644 index 0000000000..582601d335 --- /dev/null +++ b/lib/eal/loongarch/rte_cycles.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "eal_private.h" + +#define LOONGARCH_CPUCFG4 0x4 +#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF +#define CPUCFG4_CCFREQ_SHIFT 0 + +#define LOONGARCH_CPUCFG5 0x5 +#define CPUCFG5_CCMUL_MASK 0xFFFF +#define CPUCFG5_CCMUL_SHIFT 0 + +#define CPUCFG5_CCDIV_MASK 0xFFFF0000 +#define CPUCFG5_CCDIV_SHIFT 16 + +static __rte_noinline uint32_t +read_cpucfg(int arg) +{ + int ret = 0; + + __asm__ __volatile__ ( + "cpucfg %[var], %[index]\n" + : [var]"=r"(ret) + : [index]"r"(arg) + : + ); + + return ret; +} + +uint64_t +get_tsc_freq_arch(void) +{ + uint32_t base_freq, mul_factor, div_factor; + + base_freq = read_cpucfg(LOONGARCH_CPUCFG4); + mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >> + CPUCFG5_CCMUL_SHIFT; + div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >> + CPUCFG5_CCDIV_SHIFT; + + return base_freq * mul_factor / div_factor; +} -- 2.31.1