From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B47E2A04FD; Wed, 22 Jun 2022 08:48:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D1DB42B74; Wed, 22 Jun 2022 08:48:27 +0200 (CEST) Received: from smtpbg506.qq.com (smtpbg506.qq.com [203.205.250.33]) by mails.dpdk.org (Postfix) with ESMTP id 9A9BC42905 for ; Wed, 22 Jun 2022 08:48:24 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880499tafqycmf Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:18 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: +GNuArsXEgF3mRUZcS8v+Hoo6yniFzs+OQjNal7AaT770rchbfipDhlmNRjXg 0VUfTXoKb52NICrxKL/sea0yJtjDx4pLOegKt9fI+uzye16cVMNm4KFYEgtj+t/o4yZVDmM uM3olOYOdNUu2r+mktqmQXfauaORVYh51wI/VxElvhZlhmomDCZX9l91hMU1ib4Qrshzd1v tCgQ0LBK9nlydzY9KW6sY8pvDTPqAjEyt5G782cX34hvx2VgFVWrV7wiDc7wzY0mQDZ1Sjo N5LoOD3afEsaJ9TjjcZOm6/q7+nscahKeBts5saY1DELAsnQ1GpWdo2Ttg6awngj6rmaMM5 vXFbhiFsgpnOgLbOdbJJInsXd4cjhLc0a7HU1GR X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 7/7] net/ngbe: support YT PHY SGMII to RGMII mode Date: Wed, 22 Jun 2022 14:56:13 +0800 Message-Id: <20220622065613.661679-8-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign9 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add SGMII to RGMII mode for yt8521s and yt8531s PHY. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ngbe/base/ngbe_phy_yt.c | 49 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index a84c5b486b..6baa63e3bf 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -168,6 +168,7 @@ New Features * Added support for yt8531s PHY. * Added support for OEM subsystem vendor ID. * Added autoneg on/off for external PHY SFI mode. + * Added support for yt8521s/yt8531s PHY SGMII to RGMII mode. * **Updated Wangxun txgbe driver.** diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index bc1921e68a..562a0dede5 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -298,6 +298,55 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, value &= ~YT_SMI_PHY_SW_RST; ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + hw->phy.set_phy_power(hw, true); + } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(5)) { + /* sgmii_to_rgmii */ + if (!hw->mac.autoneg) { + switch (speed) { + case NGBE_LINK_SPEED_1GB_FULL: + value = YT_BCR_SPEED_SELECT1; + break; + case NGBE_LINK_SPEED_100M_FULL: + value = YT_BCR_SPEED_SELECT0; + break; + case NGBE_LINK_SPEED_10M_FULL: + value = 0; + break; + default: + value = YT_BCR_SPEED_SELECT0 | + YT_BCR_SPEED_SELECT1; + DEBUGOUT("unknown speed = 0x%x", speed); + break; + } + /* duplex full */ + value |= YT_BCR_DUPLEX | YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + goto skip_an_sr; + } + + value = 0; + if (speed & NGBE_LINK_SPEED_1GB_FULL) { + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; + value |= YT_BCR_SPEED_SELECT1; + } + if (speed & NGBE_LINK_SPEED_100M_FULL) { + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL; + value |= YT_BCR_SPEED_SELECT0; + } + if (speed & NGBE_LINK_SPEED_10M_FULL) + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL; + + /* duplex full */ + value |= YT_BCR_DUPLEX | YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + /* software reset to make the above configuration take effect */ + hw->phy.read_reg(hw, YT_BCR, 0, &value); + value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; + hw->phy.write_reg(hw, 0x0, 0, value); + +skip_an_sr: hw->phy.set_phy_power(hw, true); } -- 2.27.0