From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EFB62A0545; Thu, 30 Jun 2022 10:39:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 815E640223; Thu, 30 Jun 2022 10:39:32 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 58C08400EF for ; Thu, 30 Jun 2022 10:39:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656578371; x=1688114371; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=x1pVH5VLt3ZKNOSgRQoeVooiKbrS5ErawGheWxQBJG8=; b=A396uz4BdCseb+BC8yD7sGUUN5yoaj70kRX3pB0bI0eF9y6VqYV4gFwa awKn48uU3toC2EMEqiWx14HtMCST4t6L5t3rFxuoZo54SOuoP5G69td9q Tl87ogdqSMOOlyu5cY8eRi1xfVGC9xeS+eGSNZb/0MXqy1/yXFnHO52hM j821oqh1RuBVkQUg/a/hT2OJ78iA+Z3gHeYbtR0b1jRE+EL6IA+GQ9zB8 FfnfoIIDnfKWC5tqLGGUmyeeS68Ct8jrwTE7+2LM75FMVno0wKBC+jt+F Efj0cAqUtyBmLoZEzEVPp+ZR2zdST5YYZVqvYNyJjtx6WcbsC1pSpHGJw Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="343975953" X-IronPort-AV: E=Sophos;i="5.92,233,1650956400"; d="scan'208";a="343975953" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2022 01:39:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,233,1650956400"; d="scan'208";a="647797468" Received: from dpdk-jf-ntb-one.sh.intel.com ([10.67.110.212]) by fmsmga008.fm.intel.com with ESMTP; 30 Jun 2022 01:39:29 -0700 From: Junfeng Guo To: jingjing.wu@intel.com Cc: dev@dpdk.org, junfeng.guo@intel.com Subject: [PATCH] raw/ntb: add PPD status check for SPR Date: Thu, 30 Jun 2022 08:39:24 +0000 Message-Id: <20220630083924.175373-1-junfeng.guo@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add PPD (PCIe Port Definition) status check for SPR (Sapphire Rapids). Note that NTB on SPR has the same device id with that on ICX, while the field offsets of PPD Control Register are different. Here, we use the PCI device revision id to distinguish the HW platform (ICX/SPR) and check the Port Config Status and Port Definition accordingly. +---------------------------+--------------------+--------------------+ | Fields | Bit Range (on ICX) | Bit Range (on SPR) | +---------------------------+--------------------+--------------------+ | Port Configuration Status | 12 | 14 | | Port Definition | 9:8 | 10:8 | +---------------------------+--------------------+--------------------+ Signed-off-by: Junfeng Guo --- drivers/raw/ntb/ntb.h | 1 + drivers/raw/ntb/ntb_hw_intel.c | 60 ++++++++++++++++++++++++++++++---- drivers/raw/ntb/ntb_hw_intel.h | 13 ++++++++ 3 files changed, 68 insertions(+), 6 deletions(-) diff --git a/drivers/raw/ntb/ntb.h b/drivers/raw/ntb/ntb.h index c9ff33aa59..a30a6b60c9 100644 --- a/drivers/raw/ntb/ntb.h +++ b/drivers/raw/ntb/ntb.h @@ -19,6 +19,7 @@ extern int ntb_logtype; /* Device IDs */ #define NTB_INTEL_DEV_ID_B2B_SKX 0x201C #define NTB_INTEL_DEV_ID_B2B_ICX 0x347E +#define NTB_INTEL_DEV_ID_B2B_SPR 0x347E /* Reserved to app to use. */ #define NTB_SPAD_USER "spad_user_" diff --git a/drivers/raw/ntb/ntb_hw_intel.c b/drivers/raw/ntb/ntb_hw_intel.c index a742e8fbb9..b40142d148 100644 --- a/drivers/raw/ntb/ntb_hw_intel.c +++ b/drivers/raw/ntb/ntb_hw_intel.c @@ -37,7 +37,8 @@ is_gen3_ntb(const struct ntb_hw *hw) static inline int is_gen4_ntb(const struct ntb_hw *hw) { - if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_ICX) + if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_ICX || + hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_SPR) return 1; return 0; @@ -87,12 +88,8 @@ intel_ntb3_check_ppd(struct ntb_hw *hw) } static int -intel_ntb4_check_ppd(struct ntb_hw *hw) +intel_ntb4_check_ppd_for_ICX(struct ntb_hw *hw, uint32_t reg_val) { - uint32_t reg_val; - - reg_val = rte_read32(hw->hw_addr + XEON_GEN4_PPD1_OFFSET); - /* Check connection topo type. Only support B2B. */ switch (reg_val & XEON_GEN4_PPD_CONN_MASK) { case XEON_GEN4_PPD_CONN_B2B: @@ -115,6 +112,57 @@ intel_ntb4_check_ppd(struct ntb_hw *hw) return 0; } +static int +intel_ntb4_check_ppd_for_SPR(struct ntb_hw *hw, uint32_t reg_val) +{ + /* Check connection topo type. Only support B2B. */ + switch (reg_val & XEON_SPR_PPD_CONN_MASK) { + case XEON_SPR_PPD_CONN_B2B: + NTB_LOG(INFO, "Topo B2B (back to back) is using."); + break; + default: + NTB_LOG(ERR, "Not supported conn topo. Please use B2B."); + return -EINVAL; + } + + /* Check device type. */ + if (reg_val & XEON_SPR_PPD_DEV_DSD) { + NTB_LOG(INFO, "DSD, Downstream Device."); + hw->topo = NTB_TOPO_B2B_DSD; + } else { + NTB_LOG(INFO, "USD, Upstream device."); + hw->topo = NTB_TOPO_B2B_USD; + } + + return 0; +} + +static int +intel_ntb4_check_ppd(struct ntb_hw *hw) +{ + uint8_t revision_id; + uint32_t reg_val; + int ret; + + ret = rte_pci_read_config(hw->pci_dev, &revision_id, + NTB_PCI_DEV_REVISION_ID_LEN, + NTB_PCI_DEV_REVISION_ID_REG); + if (ret != NTB_PCI_DEV_REVISION_ID_LEN) { + NTB_LOG(ERR, "Cannot get NTB PCI Device Revision ID."); + return -EIO; + } + + reg_val = rte_read32(hw->hw_addr + XEON_GEN4_PPD1_OFFSET); + + /* Distinguish HW platform (ICX/SPR) via PCI Revision ID */ + if (revision_id > NTB_PCI_DEV_REVISION_ICX_MAX) + ret = intel_ntb4_check_ppd_for_SPR(hw, reg_val); + else if (revision_id > NTB_PCI_DEV_REVISION_ICX_MIN) + ret = intel_ntb4_check_ppd_for_ICX(hw, reg_val); + + return ret; +} + static int intel_ntb_dev_init(const struct rte_rawdev *dev) { diff --git a/drivers/raw/ntb/ntb_hw_intel.h b/drivers/raw/ntb/ntb_hw_intel.h index c61a2a8a62..9587104f80 100644 --- a/drivers/raw/ntb/ntb_hw_intel.h +++ b/drivers/raw/ntb/ntb_hw_intel.h @@ -5,6 +5,13 @@ #ifndef _NTB_HW_INTEL_H_ #define _NTB_HW_INTEL_H_ +/* Supported PCI device revision ID range for ICX */ +#define NTB_PCI_DEV_REVISION_ICX_MIN 0x02 +#define NTB_PCI_DEV_REVISION_ICX_MAX 0x0F + +#define NTB_PCI_DEV_REVISION_ID_REG 0x08 +#define NTB_PCI_DEV_REVISION_ID_LEN 1 + /* Ntb control and link status */ #define NTB_CTL_CFG_LOCK 1 #define NTB_CTL_DISABLE 2 @@ -90,6 +97,12 @@ #define XEON_GEN4_SLOTSTS 0xb05a #define XEON_GEN4_SLOTSTS_DLLSCS 0x100 +#define XEON_SPR_PPD_CONN_MASK 0x0700 +#define XEON_SPR_PPD_CONN_B2B 0x0200 +#define XEON_SPR_PPD_DEV_MASK 0x4000 +#define XEON_SPR_PPD_DEV_DSD 0x4000 +#define XEON_SPR_PPD_DEV_USD 0x0000 + #define XEON_MW_COUNT 2 #define XEON_DB_COUNT 32 -- 2.34.1