From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70959A0032; Thu, 21 Jul 2022 17:31:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0D95440141; Thu, 21 Jul 2022 17:31:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 34547400D7 for ; Thu, 21 Jul 2022 17:31:47 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26L76Pal003359; Thu, 21 Jul 2022 08:31:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=b4z6uPKndu38xxAnOwMDyEr1SQz/8jWBc9zKGvSWCk8=; b=Lh2PMn/DX2L2bgtogJUJUM84bwH8Yug3v40xgtJr5BKpu1Oh560bUqh7WIIJUsQx0yH8 TCYvR3jIRThdXU7ZMVS4j/LbXqptxkGKxdR0WcWoWL3o4t0aWWVR0ofKlL0J3Fc2/vJW JQXZgqHtV2pS35BvvfNmLL0baaxVYUFBs7In7b7u5CyENbi88IMJyezfmU0RphHvLchg Rz1bQ8Cus+yM0U9inQKqgOLZP6++dhLB1qyuNvsQF3vj5rqXIANU4+Gc8Ot10XHeQt5w JS9wFONeCOW3pmBqsvgGZig4/hwb7jxDXTOhqm0l5rISWCKY9NsW9NpQE30y9gePNClU FA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3hf2449nay-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 21 Jul 2022 08:31:46 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Jul 2022 08:31:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 21 Jul 2022 08:31:44 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id DC2353F7089; Thu, 21 Jul 2022 08:31:42 -0700 (PDT) From: Nithin Dabilpuram To: Radu Nicolau , Akhil Goyal CC: , , Nithin Dabilpuram , Subject: [PATCH 1/2] examples/ipsec-secgw: use Tx cksum offload conditionally Date: Thu, 21 Jul 2022 21:01:31 +0530 Message-ID: <20220721153132.3570-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: pNiQW9Q_bA2bQxfdKfUtTtZsWOB10SmA X-Proofpoint-ORIG-GUID: pNiQW9Q_bA2bQxfdKfUtTtZsWOB10SmA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-21_18,2022-07-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use Tx checksum offload only when all the ports have it enabled as the qconf for a particular lcore stores ipv4_offloads for all the Tx ports and each lcore can Tx to any port. Fixes: 03128be4cd4d ("examples/ipsec-secgw: allow disabling some Rx/Tx offloads") Cc: konstantin.ananyev@intel.com Signed-off-by: Nithin Dabilpuram --- examples/ipsec-secgw/ipsec-secgw.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c index 815b925..8a25b83 100644 --- a/examples/ipsec-secgw/ipsec-secgw.c +++ b/examples/ipsec-secgw/ipsec-secgw.c @@ -1998,12 +1998,6 @@ port_init(uint16_t portid, uint64_t req_rx_offloads, uint64_t req_tx_offloads) qconf = &lcore_conf[lcore_id]; qconf->tx_queue_id[portid] = tx_queueid; - /* Pre-populate pkt offloads based on capabilities */ - qconf->outbound.ipv4_offloads = RTE_MBUF_F_TX_IPV4; - qconf->outbound.ipv6_offloads = RTE_MBUF_F_TX_IPV6; - if (local_port_conf.txmode.offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) - qconf->outbound.ipv4_offloads |= RTE_MBUF_F_TX_IP_CKSUM; - tx_queueid++; /* init RX queues */ @@ -2925,6 +2919,7 @@ main(int32_t argc, char **argv) uint64_t req_rx_offloads[RTE_MAX_ETHPORTS]; uint64_t req_tx_offloads[RTE_MAX_ETHPORTS]; struct eh_conf *eh_conf = NULL; + uint32_t ipv4_cksum_port_mask = 0; size_t sess_sz; nb_bufs_in_pool = 0; @@ -3046,6 +3041,20 @@ main(int32_t argc, char **argv) &req_tx_offloads[portid]); port_init(portid, req_rx_offloads[portid], req_tx_offloads[portid]); + if ((req_tx_offloads[portid] & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) + ipv4_cksum_port_mask = 1U << portid; + } + + for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) { + if (rte_lcore_is_enabled(lcore_id) == 0) + continue; + + /* Pre-populate pkt offloads based on capabilities */ + lcore_conf[lcore_id].outbound.ipv4_offloads = RTE_MBUF_F_TX_IPV4; + lcore_conf[lcore_id].outbound.ipv6_offloads = RTE_MBUF_F_TX_IPV6; + /* Update per lcore checksum offload support only if all ports support it */ + if (ipv4_cksum_port_mask == enabled_port_mask) + lcore_conf[lcore_id].outbound.ipv4_offloads |= RTE_MBUF_F_TX_IP_CKSUM; } /* -- 2.8.4