From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D6F8A034C; Mon, 8 Aug 2022 10:07:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A50D42C6C; Mon, 8 Aug 2022 10:06:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 50B8342C6B for ; Mon, 8 Aug 2022 10:06:37 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 277NUUsj007808 for ; Mon, 8 Aug 2022 01:06:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=cPWjJna3CDXddua4ePKjNeKTn+1yfSIRoXca0BfzdKw=; b=Ffgb2HR4VaAVr/bXxzNkTnh703BwnWWoJwGJITLoP923ZEpWdQayOYBS6cDD+2UE4CPr nFbyXBHxk0eY5NGGW5gbB7KWNJHOfQC9UK/Z+4gu4ZSW+GukuumbLdYIorRNItDe0QDU vco4LwDlhAops/WIGDuwZZAw68O/I6AHOWs3AwhRTQvmnw4Rs3X0gHHy7IGHAP1kEe3W NBiHZLQmI/SafotF3Xs2zWfMFcPK5uuJhHKDOy+MALzyMAJeCGjNzE9jnUpdp/gjdeHb 2veEpvtIdDQQX9Xj+hplnCEaQy8sG1wdwwEogVC5xHZ7EkS2FsLtxmsHsiHeyN86uJ0Z 6Q== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hsqtmmxer-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 08 Aug 2022 01:06:36 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Aug 2022 01:06:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 8 Aug 2022 01:06:34 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.28.160.62]) by maili.marvell.com (Postfix) with ESMTP id A87A53F7043; Mon, 8 Aug 2022 01:06:32 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Archana Muniganti , Tejasree Kondoj , Subject: [PATCH 11/18] crypto/cnxk: avoid accessing se ctx in aes gcm path Date: Mon, 8 Aug 2022 13:35:59 +0530 Message-ID: <20220808080606.220-12-anoobj@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220808080606.220-1-anoobj@marvell.com> References: <20220808080606.220-1-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: Z5vVbpzkz1qXoNcO3GxBg4qIW18zOyZZ X-Proofpoint-ORIG-GUID: Z5vVbpzkz1qXoNcO3GxBg4qIW18zOyZZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-08_05,2022-08-05_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Field op_minor is required only for digest encrypted cases with chained ops. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cnxk_se.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 64a66ef911..55f411d50c 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -2372,8 +2372,6 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst, const bool is_kasumi) { - struct roc_se_ctx *ctx = &sess->roc_se_ctx; - uint8_t op_minor = ctx->template_w4.s.opcode_minor; struct rte_crypto_sym_op *sym_op = cop->sym; void *mdata = NULL; uint32_t mc_hash_off; @@ -2474,6 +2472,9 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, uint32_t ci_data_offset = sym_op->cipher.data.offset; uint32_t a_data_length = sym_op->auth.data.length; uint32_t a_data_offset = sym_op->auth.data.offset; + struct roc_se_ctx *ctx = &sess->roc_se_ctx; + + const uint8_t op_minor = ctx->template_w4.s.opcode_minor; d_offs = ci_data_offset; d_offs = (d_offs << 16) | a_data_offset; -- 2.25.1