From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CDF2BA034C; Mon, 8 Aug 2022 10:06:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C7B5042B8B; Mon, 8 Aug 2022 10:06:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B624242B8B for ; Mon, 8 Aug 2022 10:06:21 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 277MwkKo002933 for ; Mon, 8 Aug 2022 01:06:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=YgDaChHrDnDLfna2QxKdzmLTlajZWmcnGxvxA4+PZ4k=; b=OFIBw+DnFZP2ydWcDuNF2h7Fv+r4Wr4+Ml5hkYJFqEL5CJOpvRSCF4GQgdk5PdNyMNM8 7bKBhqWxxGDanXY/SyF97gcLLypxaPLkjwRlEespspBjVkbRrVw05QJBWs32bAWzeKtZ 8GoUkvSK5KAwAZowiwYjauBYwLuK9srCin/v+uT0AuG+5mzY99ckzfLA2Z5WSLLPDvts oTNAtMdpXW+o0dVBEbYS5WlaNdHPfyoSQ8yY6YYwVo1/SpyQNysDla4bWWga9GqjUd+p e6JZTcURTR+fUlM95AwBGqUxIWldOPOnzLIwanZu5Nz3Nvn0XnxQNWc687DUeFZlf/go oQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hsqtmmxe5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 08 Aug 2022 01:06:21 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Aug 2022 01:06:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 8 Aug 2022 01:06:18 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.28.160.62]) by maili.marvell.com (Postfix) with ESMTP id F180F3F7068; Mon, 8 Aug 2022 01:06:14 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Archana Muniganti , Tejasree Kondoj , , Volodymyr Fialko Subject: [PATCH 04/18] crypto/cnxk: limit the meta buf cache to 128 Date: Mon, 8 Aug 2022 13:35:52 +0530 Message-ID: <20220808080606.220-5-anoobj@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220808080606.220-1-anoobj@marvell.com> References: <20220808080606.220-1-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: _zdVv-CaF1EZ1KiET9UgJLl8gdgZSX83 X-Proofpoint-ORIG-GUID: _zdVv-CaF1EZ1KiET9UgJLl8gdgZSX83 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-08_05,2022-08-05_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Limit meta buf pool cache size as 128. Having 512 as the cache size would cause more time for refill. Signed-off-by: Anoob Joseph Signed-off-by: Volodymyr Fialko --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 80071872f1..a73c156d01 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -10,12 +10,13 @@ #include "cnxk_ae.h" #include "cnxk_cryptodev.h" -#include "cnxk_cryptodev_ops.h" #include "cnxk_cryptodev_capabilities.h" +#include "cnxk_cryptodev_ops.h" #include "cnxk_se.h" -#define CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS 5 -#define CNXK_CPT_MAX_ASYM_OP_MOD_LEN 1024 +#define CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS 5 +#define CNXK_CPT_MAX_ASYM_OP_MOD_LEN 1024 +#define CNXK_CPT_META_BUF_MAX_CACHE_SIZE 128 static int cnxk_cpt_get_mlen(void) @@ -200,7 +201,7 @@ cnxk_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev, } mb_pool_sz = nb_elements; - cache_sz = RTE_MIN(RTE_MEMPOOL_CACHE_MAX_SIZE, nb_elements / 1.5); + cache_sz = RTE_MIN(CNXK_CPT_META_BUF_MAX_CACHE_SIZE, nb_elements / 1.5); /* For poll mode, core that enqueues and core that dequeues can be * different. For event mode, all cores are allowed to use same crypto -- 2.25.1