From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1FE1A00C2; Tue, 9 Aug 2022 12:54:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D5E3442BCD; Tue, 9 Aug 2022 12:54:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7E5CA42BA7 for ; Tue, 9 Aug 2022 12:54:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2791FxJh015646 for ; Tue, 9 Aug 2022 03:54:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=YgDaChHrDnDLfna2QxKdzmLTlajZWmcnGxvxA4+PZ4k=; b=RR9hx9P5TRb0rxQ1K8gJP+0VCdkNfagVS+8aj8GSI2oVyG0NRt+k1zrm4fyPcsSlgrKi I0hxwV7jYNmH9aieU4LNaEHo4Ba0JzmXRh0B69vdIjgd1bvhUwgXOGHrtKTOuHAjFC0e VshwhoRjOS/g7XMOQy0Z8Zk1CH/k46yS7jvj2/eoaaaYLlFKJBRyI7BH70rmOeCJUQnq fDoDHv4GIbioUKuG74DwGpxJifXsj3mLvYcaHfP5+iPAun/s2vnB/HU1E9bB460VpVVZ souTBYpDoyV3HFExsFDrZl67JsrpmOHw/+F/9OlYNC3V3TqiCl352CxLb3ndN4g31a92 1A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2sq71-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 09 Aug 2022 03:54:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 03:54:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 03:54:10 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.70]) by maili.marvell.com (Postfix) with ESMTP id CA4D93F704C; Tue, 9 Aug 2022 03:54:07 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Archana Muniganti , Tejasree Kondoj , , Volodymyr Fialko Subject: [PATCH v2 04/18] crypto/cnxk: limit the meta buf cache to 128 Date: Tue, 9 Aug 2022 16:23:42 +0530 Message-ID: <20220809105356.561-5-anoobj@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220809105356.561-1-anoobj@marvell.com> References: <20220808080606.220-1-anoobj@marvell.com> <20220809105356.561-1-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: wmqDh3fWUqw4G7siiFDSkNtCuIWwYAd7 X-Proofpoint-GUID: wmqDh3fWUqw4G7siiFDSkNtCuIWwYAd7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_03,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Limit meta buf pool cache size as 128. Having 512 as the cache size would cause more time for refill. Signed-off-by: Anoob Joseph Signed-off-by: Volodymyr Fialko --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 80071872f1..a73c156d01 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -10,12 +10,13 @@ #include "cnxk_ae.h" #include "cnxk_cryptodev.h" -#include "cnxk_cryptodev_ops.h" #include "cnxk_cryptodev_capabilities.h" +#include "cnxk_cryptodev_ops.h" #include "cnxk_se.h" -#define CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS 5 -#define CNXK_CPT_MAX_ASYM_OP_MOD_LEN 1024 +#define CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS 5 +#define CNXK_CPT_MAX_ASYM_OP_MOD_LEN 1024 +#define CNXK_CPT_META_BUF_MAX_CACHE_SIZE 128 static int cnxk_cpt_get_mlen(void) @@ -200,7 +201,7 @@ cnxk_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev, } mb_pool_sz = nb_elements; - cache_sz = RTE_MIN(RTE_MEMPOOL_CACHE_MAX_SIZE, nb_elements / 1.5); + cache_sz = RTE_MIN(CNXK_CPT_META_BUF_MAX_CACHE_SIZE, nb_elements / 1.5); /* For poll mode, core that enqueues and core that dequeues can be * different. For event mode, all cores are allowed to use same crypto -- 2.25.1