From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8915DA0542; Mon, 29 Aug 2022 17:17:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 509294282F; Mon, 29 Aug 2022 17:17:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C87314003C for ; Mon, 29 Aug 2022 17:17:34 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27T7fUrJ010634; Mon, 29 Aug 2022 08:17:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=gCTtDTWcUaOcCDYgHl29AwWuOsmn3Z/ZKP9P/p2JEVA=; b=BVR9NQ8xmPRrUD6Dvb6YtIVDuYMGRH0Juot0Q50mb6Uh9FJaArqWYBdsDEZG2S288y1s 3A80LAyPzb9O6bGoYKtI8mZ63Yv1cOLh9GUZ1DoWoieQcj1zdZQoZnZMQscLu2uagw0Q 8oxtbAorkdMkutqIc2K4bOe66cVRR27i5mRHQxNlb+Q5+OP/9x5TFedSQAOyaMcRJRko x5wRjHwHhf0CWv2sVfHohv6nCABADXbvWqp+6iuBMbG1/wNWDeyVYVjQ8xhR3v2TmFw+ bng4hFSOYAmx9+ciLulmz4YbjzhIsEaCjgOT2fjcsmaYpsi5wqALLt1GtBmOHsZPD1M6 Ww== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3j7jsn7u03-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 29 Aug 2022 08:17:31 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 29 Aug 2022 08:17:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 29 Aug 2022 08:17:29 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 098F03F7068; Mon, 29 Aug 2022 08:17:26 -0700 (PDT) From: Shijith Thotton To: CC: , Shijith Thotton , , , , , , , Subject: [PATCH v1 2/4] mbuf: add second dynamic field member for VA only build Date: Mon, 29 Aug 2022 20:46:23 +0530 Message-ID: <20220829151626.2101336-3-sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: pJlp0RtJM9K-sqVanUtiKywy2p_sqoEq X-Proofpoint-GUID: pJlp0RtJM9K-sqVanUtiKywy2p_sqoEq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-29_07,2022-08-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org mbuf physical address field is not used in builds which only uses VA. It is used to expand the dynamic field area. Signed-off-by: Shijith Thotton --- lib/mbuf/rte_mbuf_core.h | 26 +++++++++++++++++--------- lib/mbuf/rte_mbuf_dyn.c | 2 ++ 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/lib/mbuf/rte_mbuf_core.h b/lib/mbuf/rte_mbuf_core.h index 81cb07c2e4..98ce62fd6a 100644 --- a/lib/mbuf/rte_mbuf_core.h +++ b/lib/mbuf/rte_mbuf_core.h @@ -579,15 +579,23 @@ struct rte_mbuf { RTE_MARKER cacheline0; void *buf_addr; /**< Virtual address of segment buffer. */ - /** - * Physical address of segment buffer. - * This field is invalid if the build is configured to use only - * virtual address as IOVA (i.e. RTE_IOVA_AS_VA is defined). - * Force alignment to 8-bytes, so as to ensure we have the exact - * same mbuf cacheline0 layout for 32-bit and 64-bit. This makes - * working on vector drivers easier. - */ - rte_iova_t buf_iova __rte_aligned(sizeof(rte_iova_t)); + RTE_STD_C11 + union { + /** + * Physical address of segment buffer. + * This field is invalid if the build is configured to use only + * virtual address as IOVA (i.e. RTE_IOVA_AS_VA is defined). + * Force alignment to 8-bytes, so as to ensure we have the exact + * same mbuf cacheline0 layout for 32-bit and 64-bit. This makes + * working on vector drivers easier. + */ + rte_iova_t buf_iova __rte_aligned(sizeof(rte_iova_t)); + /** + * Reserved for dynamic field in builds where physical address + * field is invalid. + */ + uint64_t dynfield2; + }; /* next 8 bytes are initialised on RX descriptor rearm */ RTE_MARKER64 rearm_data; diff --git a/lib/mbuf/rte_mbuf_dyn.c b/lib/mbuf/rte_mbuf_dyn.c index 4ae79383b5..0813d5fb34 100644 --- a/lib/mbuf/rte_mbuf_dyn.c +++ b/lib/mbuf/rte_mbuf_dyn.c @@ -128,6 +128,8 @@ init_shared_mem(void) */ memset(shm, 0, sizeof(*shm)); mark_free(dynfield1); + if (rte_is_iova_as_va_build()) + mark_free(dynfield2); /* init free_flags */ for (mask = RTE_MBUF_F_FIRST_FREE; mask <= RTE_MBUF_F_LAST_FREE; mask <<= 1) -- 2.25.1