From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 28B35A054F; Wed, 7 Sep 2022 15:44:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1C3C8427F1; Wed, 7 Sep 2022 15:44:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C0BB3400D6 for ; Wed, 7 Sep 2022 15:44:22 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 287ABlYZ029526; Wed, 7 Sep 2022 06:44:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=YNeUeH30tkr+BRq4AuIddvsTQcmFFaTITsQkblIdMqI=; b=GkSfwm6H6CJ7T8cFHj6SgTiRb+sI7z8iuGiNWP1eo/WwXpt91bgJfpJOocenTo+a92q/ wHbEsOlGkaKDyk2xizkAJgc3gnDOdDqVQB/sUrk8gQgBLXSBhB7j2mmfPrxZiJYdZVzb bOwdV41fOrP6WUBZc3aZY221dKE1B55ANKn/cW3pFBPcuq7dxb5YUiBDhpWoPATCG/MZ 0fhvHJNbwVHELvQeCqn/LvGJjSXBuZjH7jyJ9p3bMYCFR3WEN/4rDb+rO/3uRVtiBzCM huG7uhD12v2TYst1BgaXMylqmvpPFEbN8qVDsuK1XlfoI1TcxjHtT7CoC4E4DkINeuMi vw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jc6epxg65-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 07 Sep 2022 06:44:17 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Sep 2022 06:44:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 7 Sep 2022 06:44:15 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 911463F7081; Wed, 7 Sep 2022 06:44:12 -0700 (PDT) From: Shijith Thotton To: CC: , Shijith Thotton , , , , , , , Subject: [PATCH v2 2/5] mbuf: add second dynamic field member for VA only build Date: Wed, 7 Sep 2022 19:13:37 +0530 Message-ID: <20220907134340.3629224-3-sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220829151626.2101336-1-sthotton@marvell.com> References: <20220829151626.2101336-1-sthotton@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: ati6VNVzDkGX5TWZjNWIxc56A9R3QhNW X-Proofpoint-GUID: ati6VNVzDkGX5TWZjNWIxc56A9R3QhNW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-07_08,2022-09-07_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org mbuf physical address field is not used in builds which only uses VA. It is used to expand the dynamic field area. Signed-off-by: Shijith Thotton --- lib/mbuf/rte_mbuf_core.h | 26 +++++++++++++++++--------- lib/mbuf/rte_mbuf_dyn.c | 2 ++ 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/lib/mbuf/rte_mbuf_core.h b/lib/mbuf/rte_mbuf_core.h index c6292e7252..94907f301d 100644 --- a/lib/mbuf/rte_mbuf_core.h +++ b/lib/mbuf/rte_mbuf_core.h @@ -579,15 +579,23 @@ struct rte_mbuf { RTE_MARKER cacheline0; void *buf_addr; /**< Virtual address of segment buffer. */ - /** - * Physical address of segment buffer. - * This field is invalid if the build is configured to use only - * virtual address as IOVA (i.e. RTE_IOVA_AS_VA is 1). - * Force alignment to 8-bytes, so as to ensure we have the exact - * same mbuf cacheline0 layout for 32-bit and 64-bit. This makes - * working on vector drivers easier. - */ - rte_iova_t buf_iova __rte_aligned(sizeof(rte_iova_t)); + RTE_STD_C11 + union { + /** + * Physical address of segment buffer. + * This field is invalid if the build is configured to use only + * virtual address as IOVA (i.e. RTE_IOVA_AS_VA is 1). + * Force alignment to 8-bytes, so as to ensure we have the exact + * same mbuf cacheline0 layout for 32-bit and 64-bit. This makes + * working on vector drivers easier. + */ + rte_iova_t buf_iova __rte_aligned(sizeof(rte_iova_t)); + /** + * Reserved for dynamic field in builds where physical address + * field is invalid. + */ + uint64_t dynfield2; + }; /* next 8 bytes are initialised on RX descriptor rearm */ RTE_MARKER64 rearm_data; diff --git a/lib/mbuf/rte_mbuf_dyn.c b/lib/mbuf/rte_mbuf_dyn.c index 4ae79383b5..6a4cf96897 100644 --- a/lib/mbuf/rte_mbuf_dyn.c +++ b/lib/mbuf/rte_mbuf_dyn.c @@ -128,6 +128,8 @@ init_shared_mem(void) */ memset(shm, 0, sizeof(*shm)); mark_free(dynfield1); + if (RTE_IOVA_AS_VA) + mark_free(dynfield2); /* init free_flags */ for (mask = RTE_MBUF_F_FIRST_FREE; mask <= RTE_MBUF_F_LAST_FREE; mask <<= 1) -- 2.25.1