From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 530E4A00C2; Tue, 27 Sep 2022 00:55:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 59D9D427F0; Tue, 27 Sep 2022 00:55:46 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 43B9740146 for ; Tue, 27 Sep 2022 00:55:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664232943; x=1695768943; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VkabtjjukNabY6kku20RObaxlU9mXIoYFE3pxHo0LkA=; b=I3PMDeMYM7p0dVNvpy7R/zI7+QrGsCyFXtyfjyyR7QKNGU1Wk9ITufbW MzA1Zgz6ECDpOhJz/i6ZlbY6sFzmKqv9ov6BGtmi3CTwj7ONPGdNAcY5m mF/ILJjBoTeLdy5WJJo9Caf/GVGZxZiWvkRdCI8bnhYanY+zyYhfZIn2T G339DXgdDjHqzosBBGmoA3TtXXLVF45Uptag6GodbhXjW2G3jwpqd1NQc yaQICuKpJqkwryB1Rwze9msY4lT5Bw7NTe4Wy+22MzJcaIQeh3NWBDCDX v3apLggozkr8PnW+XYU6rdy1kcN3HEscsMhOy7ROEElcI9Zw38p40VU7i g==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="302067148" X-IronPort-AV: E=Sophos;i="5.93,347,1654585200"; d="scan'208";a="302067148" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 15:55:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="746807152" X-IronPort-AV: E=Sophos;i="5.93,347,1654585200"; d="scan'208";a="746807152" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga004.jf.intel.com with ESMTP; 26 Sep 2022 15:55:42 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, rashmi.shetty@intel.com, pravin.pathak@intel.com, mike.ximing.chen@intel.com, timothy.mcdaniel@intel.com, shivani.doneria@intel.com, tirthendu.sarkar@intel.com, Abdullah Sevincer Subject: [PATCH v3 2/3] event/dlb2: add fence bypass option for producer ports Date: Mon, 26 Sep 2022 17:55:35 -0500 Message-Id: <20220926225536.1387161-2-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220926225536.1387161-1-abdullah.sevincer@intel.com> References: <20220820005957.2986689-2-timothy.mcdaniel@intel.com> <20220926225536.1387161-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org If producer thread is only acting as a bridge between NIC and DLB, then performance can be greatly improved by bypassing the fence instruction. DLB enqueue API calls memory fence once per enqueue burst. If prodcuer thread is just reading from NIC and sending to DLB without updating the read buffers or buffer headers OR producer is not writing to data structures with dependencies on the enqueue write order, then fencing can be safely disabled. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/dlb2.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 6a9db4b642..4dd1d55ddc 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -35,6 +35,16 @@ #include "dlb2_iface.h" #include "dlb2_inline_fns.h" +/* + * Bypass memory fencing instructions when port is of Producer type. + * This should be enabled very carefully with understanding that producer + * is not doing any writes which need fencing. The movdir64 instruction used to + * enqueue events to DLB is a weakly-ordered instruction and movdir64 write + * to DLB can go ahead of relevant application writes like updates to buffers + * being sent with event + */ +#define DLB2_BYPASS_FENCE_ON_PP 0 /* 1 == Bypass fence, 0 == do not bypass */ + /* * Resources exposed to eventdev. Some values overridden at runtime using * values returned by the DLB kernel driver. @@ -1985,21 +1995,15 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev, sw_credit_quanta = dlb2->sw_credit_quanta; hw_credit_quanta = dlb2->hw_credit_quanta; + ev_port->qm_port.is_producer = false; ev_port->qm_port.is_directed = port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_SINGLE_LINK; - /* - * Validate credit config before creating port - */ - - /* Default for worker ports */ - sw_credit_quanta = dlb2->sw_credit_quanta; - hw_credit_quanta = dlb2->hw_credit_quanta; - if (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_PRODUCER) { /* Producer type ports. Mostly enqueue */ sw_credit_quanta = DLB2_SW_CREDIT_P_QUANTA_DEFAULT; hw_credit_quanta = DLB2_SW_CREDIT_P_BATCH_SZ; + ev_port->qm_port.is_producer = true; } if (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_CONSUMER) { /* Consumer type ports. Mostly dequeue */ @@ -2009,6 +2013,10 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev, ev_port->credit_update_quanta = sw_credit_quanta; ev_port->qm_port.hw_credit_quanta = hw_credit_quanta; + /* + * Validate credit config before creating port + */ + if (port_conf->enqueue_depth > sw_credit_quanta || port_conf->enqueue_depth > hw_credit_quanta) { DLB2_LOG_ERR("Invalid port config. Enqueue depth %d must be <= credit quanta %d and batch size %d\n", @@ -3073,7 +3081,12 @@ __dlb2_event_enqueue_burst(void *event_port, dlb2_event_build_hcws(qm_port, &events[i], j - pop_offs, sched_types, queue_ids); +#if DLB2_BYPASS_FENCE_ON_PP == 1 + /* Bypass fence instruction for producer ports */ + dlb2_hw_do_enqueue(qm_port, i == 0 && !qm_port->is_producer, port_data); +#else dlb2_hw_do_enqueue(qm_port, i == 0, port_data); +#endif /* Don't include the token pop QE in the enqueue count */ i += j - pop_offs; -- 2.25.1