From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB807A00C2; Tue, 27 Sep 2022 10:00:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BBEDE410D0; Tue, 27 Sep 2022 10:00:17 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 31B5B40696 for ; Tue, 27 Sep 2022 10:00:16 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28R491aE031941 for ; Tue, 27 Sep 2022 01:00:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6B3gJyVLFM3Rx+H6L4dVUT3g6UY3vOSm63CZ2pJzYfM=; b=ib+wK08QfFcRWh96j2SqIDfWtjlhL1pkKnh9vux7NsGuPJGrG8pdKh6fQzscPt1mL6wA N3SnIXVMkmOLCbfu2z5/MmHGCQhI3igxtFtYjg3Ifflg+B6BLqJRiDIRhxBZMa0waBkf O0pH4cJHPPbb4UKy7C8tqOCCbeEdlckRtvNJmss5ummJvqCiLMt7Ttswl4zMHCH5ggQD O3bMvoGK7+j3GYoUdvNh6EtUuWhjqv7jrJ2QqfETGL+q5BY0FZrmNivfvvtG3G3DDEiP I9OZtTKVUmvTZTz89Tw8qUa7VMyi1rQs988gdTne2/agHYojuBWGUG+n5+Z4mQW2odx8 Nw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3jucsq39ng-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 27 Sep 2022 01:00:15 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Sep 2022 01:00:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 27 Sep 2022 01:00:13 -0700 Received: from localhost.localdomain (unknown [10.28.34.38]) by maili.marvell.com (Postfix) with ESMTP id C1DAB3F70D1; Tue, 27 Sep 2022 01:00:09 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: Anoob Joseph , Ankur Dwivedi , Tejasree Kondoj , Akhil Goyal , , Gowrishankar Muthukrishnan Subject: [v1] crypto/cnxk: support exponent type private key Date: Tue, 27 Sep 2022 13:30:05 +0530 Message-ID: <20220927080005.3667317-1-gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: jiFNbeYdMyKoyeb9IrkShv8ftpSK5nCM X-Proofpoint-ORIG-GUID: jiFNbeYdMyKoyeb9IrkShv8ftpSK5nCM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-27_02,2022-09-22_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds support for RTE_RSA_KEY_TYPE_EXP in cnxk crypto driver. Signed-off-by: Gowrishankar Muthukrishnan --- drivers/crypto/cnxk/cnxk_ae.h | 60 ++++++++++++++++++++++------ drivers/crypto/cnxk/cnxk_cryptodev.c | 1 + 2 files changed, 48 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h index 4a7ce0bf40..7a61c81cfd 100644 --- a/drivers/crypto/cnxk/cnxk_ae.h +++ b/drivers/crypto/cnxk/cnxk_ae.h @@ -82,6 +82,7 @@ cnxk_ae_fill_rsa_params(struct cnxk_ae_sess *sess, struct rte_crypto_rsa_priv_key_qt qt = xform->rsa.qt; struct rte_crypto_rsa_xform *xfrm_rsa = &xform->rsa; struct rte_crypto_rsa_xform *rsa = &sess->rsa_ctx; + struct rte_crypto_param_t d = xform->rsa.d; size_t mod_len = xfrm_rsa->n.length; size_t exp_len = xfrm_rsa->e.length; uint64_t total_size; @@ -90,12 +91,20 @@ cnxk_ae_fill_rsa_params(struct cnxk_ae_sess *sess, if (qt.p.length != 0 && qt.p.data == NULL) return -EINVAL; + /* Set private key type */ + rsa->key_type = xfrm_rsa->key_type; + /* Make sure key length used is not more than mod_len/2 */ - if (qt.p.data != NULL) - len = (((mod_len / 2) < qt.p.length) ? 0 : qt.p.length); + if (rsa->key_type == RTE_RSA_KEY_TYPE_QT) { + if (qt.p.data != NULL) + len = (((mod_len / 2) < qt.p.length) ? 0 : qt.p.length * 5); + } else if (rsa->key_type == RTE_RSA_KEY_TYPE_EXP) { + if (d.length != 0) + len = d.length - exp_len; + } /* Total size required for RSA key params(n,e,(q,dQ,p,dP,qInv)) */ - total_size = mod_len + exp_len + 5 * len; + total_size = mod_len + exp_len + len; /* Allocate buffer to hold all RSA keys */ rsa->n.data = rte_malloc(NULL, total_size, 0); @@ -107,8 +116,8 @@ cnxk_ae_fill_rsa_params(struct cnxk_ae_sess *sess, rsa->e.data = rsa->n.data + mod_len; memcpy(rsa->e.data, xfrm_rsa->e.data, exp_len); - /* Private key in quintuple format */ - if (len != 0) { + if (rsa->key_type == RTE_RSA_KEY_TYPE_QT) { + /* Private key in quintuple format */ rsa->qt.q.data = rsa->e.data + exp_len; memcpy(rsa->qt.q.data, qt.q.data, qt.q.length); rsa->qt.dQ.data = rsa->qt.q.data + qt.q.length; @@ -126,6 +135,14 @@ cnxk_ae_fill_rsa_params(struct cnxk_ae_sess *sess, rsa->qt.p.length = qt.p.length; rsa->qt.dP.length = qt.dP.length; rsa->qt.qInv.length = qt.qInv.length; + } else if (d.length != 0) { + /* Private key in exponent format */ + rsa->d.data = rte_malloc(NULL, d.length, 0); + if (rsa->d.data == NULL) + return -ENOMEM; + + memcpy(rsa->d.data, d.data, d.length); + rsa->d.length = d.length; } rsa->n.length = mod_len; rsa->e.length = exp_len; @@ -200,6 +217,8 @@ cnxk_ae_free_session_parameters(struct cnxk_ae_sess *sess) case RTE_CRYPTO_ASYM_XFORM_RSA: rsa = &sess->rsa_ctx; rte_free(rsa->n.data); + if (rsa->key_type == RTE_RSA_KEY_TYPE_EXP) + rte_free(rsa->d.data); break; case RTE_CRYPTO_ASYM_XFORM_MODEX: mod = &sess->mod_ctx; @@ -295,12 +314,14 @@ cnxk_ae_rsa_prep(struct rte_crypto_op *op, struct roc_ae_buf_ptr *meta_buf, w4.s.opcode_minor = ROC_AE_MINOR_OP_MODEX; w4.s.param2 = exp_len; } else { - if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT) { + if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT || + rsa_op.op_type == RTE_CRYPTO_ASYM_OP_SIGN) { w4.s.opcode_minor = ROC_AE_MINOR_OP_PKCS_ENC; /* Public key encrypt, use BT2*/ w4.s.param2 = ROC_AE_CPT_BLOCK_TYPE2 | ((uint16_t)(exp_len) << 1); - } else if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_VERIFY) { + } else if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_VERIFY || + rsa_op.op_type == RTE_CRYPTO_ASYM_OP_DECRYPT) { w4.s.opcode_minor = ROC_AE_MINOR_OP_PKCS_DEC; /* Public key decrypt, use BT1 */ w4.s.param2 = ROC_AE_CPT_BLOCK_TYPE1; @@ -379,23 +400,36 @@ cnxk_ae_enqueue_rsa_op(struct rte_crypto_op *op, struct cnxk_ae_sess *sess, struct cpt_inst_s *inst) { struct rte_crypto_rsa_op_param *rsa = &op->asym->rsa; + struct rte_crypto_rsa_xform *ctx = &sess->rsa_ctx; switch (rsa->op_type) { case RTE_CRYPTO_ASYM_OP_VERIFY: - cnxk_ae_rsa_prep(op, meta_buf, &sess->rsa_ctx, &rsa->sign, + cnxk_ae_rsa_prep(op, meta_buf, ctx, &rsa->sign, inst); break; case RTE_CRYPTO_ASYM_OP_ENCRYPT: - cnxk_ae_rsa_prep(op, meta_buf, &sess->rsa_ctx, &rsa->message, + cnxk_ae_rsa_prep(op, meta_buf, ctx, &rsa->message, inst); break; case RTE_CRYPTO_ASYM_OP_SIGN: - cnxk_ae_rsa_crt_prep(op, meta_buf, &sess->rsa_ctx, - &rsa->message, inst); + if (ctx->key_type == RTE_RSA_KEY_TYPE_QT) { + cnxk_ae_rsa_crt_prep(op, meta_buf, ctx, &rsa->message, inst); + } else { + memcpy(ctx->e.data, ctx->d.data, ctx->d.length); + ctx->e.length = ctx->d.length; + cnxk_ae_rsa_prep(op, meta_buf, ctx, + &rsa->message, inst); + } break; case RTE_CRYPTO_ASYM_OP_DECRYPT: - cnxk_ae_rsa_crt_prep(op, meta_buf, &sess->rsa_ctx, &rsa->cipher, - inst); + if (ctx->key_type == RTE_RSA_KEY_TYPE_QT) { + cnxk_ae_rsa_crt_prep(op, meta_buf, ctx, &rsa->cipher, inst); + } else { + memcpy(ctx->e.data, ctx->d.data, ctx->d.length); + ctx->e.length = ctx->d.length; + cnxk_ae_rsa_prep(op, meta_buf, ctx, + &rsa->cipher, inst); + } break; default: op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.c b/drivers/crypto/cnxk/cnxk_cryptodev.c index d67de54a7b..35635f7831 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev.c @@ -15,6 +15,7 @@ cnxk_cpt_default_ff_get(void) RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT | + RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_EXP | RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | -- 2.25.1