From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D687A00C5; Thu, 29 Sep 2022 07:03:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 432FC427F5; Thu, 29 Sep 2022 07:03:16 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id B2BD540FAE for ; Thu, 29 Sep 2022 07:03:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664427792; x=1695963792; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VkabtjjukNabY6kku20RObaxlU9mXIoYFE3pxHo0LkA=; b=O0a5Auy1Nj8LT4KIawdXkoHDcNDVocil4pYTAvnLhoorgJ+9v+CFMG9W IzXczowMgJPqYLoSN981aRB7PFmabywtuEZuTl8iBG/pdCIR2oCda+Oab s992ItNy3flfxrsdD8PX+dTiZTXnm5QPNQ1NWeNLHv4IDecw8NuwBaZ4x ReYcReREKVJsMcjkyePkc74CA1MkWQM9T88vmS6KEp9hepgBGe4Sg5fgO 842J3bFGstYipceCJSZxW+gxShbfR2ZSDpkhsOturRZe1ZEiacQJ/m+Xv VFIvRc8ZpQoI6nJd9bKSMCRt5JbHIvHZ2IVLz3+WZ7kSJXB/H6p8fEVkz g==; X-IronPort-AV: E=McAfee;i="6500,9779,10484"; a="284928578" X-IronPort-AV: E=Sophos;i="5.93,354,1654585200"; d="scan'208";a="284928578" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2022 22:03:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10484"; a="797417388" X-IronPort-AV: E=Sophos;i="5.93,354,1654585200"; d="scan'208";a="797417388" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga005.jf.intel.com with ESMTP; 28 Sep 2022 22:03:07 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, Abdullah Sevincer Subject: [PATCH v10 2/3] event/dlb2: add fence bypass option for producer ports Date: Thu, 29 Sep 2022 00:03:03 -0500 Message-Id: <20220929050304.1678012-2-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220929050304.1678012-1-abdullah.sevincer@intel.com> References: <20220820005957.2986689-2-timothy.mcdaniel@intel.com> <20220929050304.1678012-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org If producer thread is only acting as a bridge between NIC and DLB, then performance can be greatly improved by bypassing the fence instruction. DLB enqueue API calls memory fence once per enqueue burst. If prodcuer thread is just reading from NIC and sending to DLB without updating the read buffers or buffer headers OR producer is not writing to data structures with dependencies on the enqueue write order, then fencing can be safely disabled. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/dlb2.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 6a9db4b642..4dd1d55ddc 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -35,6 +35,16 @@ #include "dlb2_iface.h" #include "dlb2_inline_fns.h" +/* + * Bypass memory fencing instructions when port is of Producer type. + * This should be enabled very carefully with understanding that producer + * is not doing any writes which need fencing. The movdir64 instruction used to + * enqueue events to DLB is a weakly-ordered instruction and movdir64 write + * to DLB can go ahead of relevant application writes like updates to buffers + * being sent with event + */ +#define DLB2_BYPASS_FENCE_ON_PP 0 /* 1 == Bypass fence, 0 == do not bypass */ + /* * Resources exposed to eventdev. Some values overridden at runtime using * values returned by the DLB kernel driver. @@ -1985,21 +1995,15 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev, sw_credit_quanta = dlb2->sw_credit_quanta; hw_credit_quanta = dlb2->hw_credit_quanta; + ev_port->qm_port.is_producer = false; ev_port->qm_port.is_directed = port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_SINGLE_LINK; - /* - * Validate credit config before creating port - */ - - /* Default for worker ports */ - sw_credit_quanta = dlb2->sw_credit_quanta; - hw_credit_quanta = dlb2->hw_credit_quanta; - if (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_PRODUCER) { /* Producer type ports. Mostly enqueue */ sw_credit_quanta = DLB2_SW_CREDIT_P_QUANTA_DEFAULT; hw_credit_quanta = DLB2_SW_CREDIT_P_BATCH_SZ; + ev_port->qm_port.is_producer = true; } if (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_CONSUMER) { /* Consumer type ports. Mostly dequeue */ @@ -2009,6 +2013,10 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev, ev_port->credit_update_quanta = sw_credit_quanta; ev_port->qm_port.hw_credit_quanta = hw_credit_quanta; + /* + * Validate credit config before creating port + */ + if (port_conf->enqueue_depth > sw_credit_quanta || port_conf->enqueue_depth > hw_credit_quanta) { DLB2_LOG_ERR("Invalid port config. Enqueue depth %d must be <= credit quanta %d and batch size %d\n", @@ -3073,7 +3081,12 @@ __dlb2_event_enqueue_burst(void *event_port, dlb2_event_build_hcws(qm_port, &events[i], j - pop_offs, sched_types, queue_ids); +#if DLB2_BYPASS_FENCE_ON_PP == 1 + /* Bypass fence instruction for producer ports */ + dlb2_hw_do_enqueue(qm_port, i == 0 && !qm_port->is_producer, port_data); +#else dlb2_hw_do_enqueue(qm_port, i == 0, port_data); +#endif /* Don't include the token pop QE in the enqueue count */ i += j - pop_offs; -- 2.25.1