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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT013.mail.protection.outlook.com (10.13.176.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 15:04:08 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 08:03:57 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 08:03:54 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , , Bing Zhao Subject: [v2 05/19] common/mlx5: query set capability of registers Date: Thu, 6 Oct 2022 18:03:11 +0300 Message-ID: <20221006150325.660-6-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221006150325.660-1-valex@nvidia.com> References: <20220922190345.394-1-valex@nvidia.com> <20221006150325.660-1-valex@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT013:EE_|MN0PR12MB5956:EE_ X-MS-Office365-Filtering-Correlation-Id: d4665a12-6f98-465f-5ce2-08daa7ac0549 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 15:04:08.8910 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4665a12-6f98-465f-5ce2-08daa7ac0549 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5956 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Bing Zhao In the flow table capabilities, new fields are added to query the capability to set, add, copy to a REG_C_x. The set capability are queried and saved for the future usage. Signed-off-by: Bing Zhao --- drivers/common/mlx5/mlx5_devx_cmds.c | 30 +++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 44 +++++++++++++++++++++++++--- 3 files changed, 72 insertions(+), 4 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index fb33023138..ac6891145d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1058,6 +1058,24 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->modify_outer_ip_ecn = MLX5_GET (flow_table_nic_cap, hcattr, ft_header_modify_nic_receive.outer_ip_ecn); + attr->set_reg_c = 0xff; + if (attr->nic_flow_table) { +#define GET_RX_REG_X_BITS \ + MLX5_GET(flow_table_nic_cap, hcattr, \ + ft_header_modify_nic_receive.metadata_reg_c_x) +#define GET_TX_REG_X_BITS \ + MLX5_GET(flow_table_nic_cap, hcattr, \ + ft_header_modify_nic_transmit.metadata_reg_c_x) + + uint32_t tx_reg, rx_reg; + + tx_reg = GET_TX_REG_X_BITS; + rx_reg = GET_RX_REG_X_BITS; + attr->set_reg_c &= (rx_reg & tx_reg); + +#undef GET_RX_REG_X_BITS +#undef GET_TX_REG_X_BITS + } attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); attr->inner_ipv4_ihl = MLX5_GET (flow_table_nic_cap, hcattr, @@ -1157,6 +1175,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->esw_mgr_vport_id = MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); } + if (attr->eswitch_manager) { + uint32_t esw_reg; + + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; + esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, + ft_header_modify_esw_fdb.metadata_reg_c_x); + attr->set_reg_c &= esw_reg; + } return 0; error: rc = (rc > 0) ? -rc : rc; diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index af6053a788..d69dad613e 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -260,6 +260,8 @@ struct mlx5_hca_attr { uint32_t crypto_wrapped_import_method:1; uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ uint16_t max_wqe_sz_sq; + uint32_t set_reg_c:8; + uint32_t nic_flow_table:1; uint32_t modify_outer_ip_ecn:1; }; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 4346279c81..12eb7b3b7f 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1892,6 +1892,7 @@ struct mlx5_ifc_roce_caps_bits { }; struct mlx5_ifc_ft_fields_support_bits { + /* set_action_field_support */ u8 outer_dmac[0x1]; u8 outer_smac[0x1]; u8 outer_ether_type[0x1]; @@ -1919,7 +1920,7 @@ struct mlx5_ifc_ft_fields_support_bits { u8 outer_gre_key[0x1]; u8 outer_vxlan_vni[0x1]; u8 reserved_at_1a[0x5]; - u8 source_eswitch_port[0x1]; + u8 source_eswitch_port[0x1]; /* end of DW0 */ u8 inner_dmac[0x1]; u8 inner_smac[0x1]; u8 inner_ether_type[0x1]; @@ -1943,8 +1944,33 @@ struct mlx5_ifc_ft_fields_support_bits { u8 inner_tcp_sport[0x1]; u8 inner_tcp_dport[0x1]; u8 inner_tcp_flags[0x1]; - u8 reserved_at_37[0x9]; - u8 reserved_at_40[0x40]; + u8 reserved_at_37[0x9]; /* end of DW1 */ + u8 reserved_at_40[0x20]; /* end of DW2 */ + u8 reserved_at_60[0x18]; + union { + struct { + u8 metadata_reg_c_7[0x1]; + u8 metadata_reg_c_6[0x1]; + u8 metadata_reg_c_5[0x1]; + u8 metadata_reg_c_4[0x1]; + u8 metadata_reg_c_3[0x1]; + u8 metadata_reg_c_2[0x1]; + u8 metadata_reg_c_1[0x1]; + u8 metadata_reg_c_0[0x1]; + }; + u8 metadata_reg_c_x[0x8]; + }; /* end of DW3 */ + /* set_action_field_support_2 */ + u8 reserved_at_80[0x80]; + /* add_action_field_support */ + u8 reserved_at_100[0x80]; + /* add_action_field_support_2 */ + u8 reserved_at_180[0x80]; + /* copy_action_field_support */ + u8 reserved_at_200[0x80]; + /* copy_action_field_support_2 */ + u8 reserved_at_280[0x80]; + u8 reserved_at_300[0x100]; }; /* @@ -1989,9 +2015,18 @@ struct mlx5_ifc_flow_table_nic_cap_bits { u8 reserved_at_e00[0x200]; struct mlx5_ifc_ft_fields_support_bits ft_header_modify_nic_receive; - u8 reserved_at_1080[0x380]; struct mlx5_ifc_ft_fields_support_2_bits ft_field_support_2_nic_receive; + u8 reserved_at_1480[0x780]; + struct mlx5_ifc_ft_fields_support_bits + ft_header_modify_nic_transmit; + u8 reserved_at_2000[0x6000]; +}; + +struct mlx5_ifc_flow_table_esw_cap_bits { + u8 reserved_at_0[0x800]; + struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb; + u8 reserved_at_C00[0x7400]; }; /* @@ -2041,6 +2076,7 @@ union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_qos_cap_bits qos_cap; struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; + struct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap; struct mlx5_ifc_esw_cap_bits esw_cap; struct mlx5_ifc_roce_caps_bits roce_caps; u8 reserved_at_0[0x8000]; -- 2.18.1