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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT050.mail.protection.outlook.com (10.13.174.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Fri, 7 Oct 2022 17:44:48 +0000 Received: from driver-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Fri, 7 Oct 2022 12:44:47 -0500 From: Andrew Boyer To: CC: Andrew Boyer Subject: [PATCH 18/35] net/ionic: do one-time init of receive descriptors Date: Fri, 7 Oct 2022 10:43:19 -0700 Message-ID: <20221007174336.54354-19-andrew.boyer@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221007174336.54354-1-andrew.boyer@amd.com> References: <20221007174336.54354-1-andrew.boyer@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT050:EE_|DM6PR12MB4387:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f8269bc-dcb4-4734-3e5e-08daa88ba10e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This improves performance. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_rxtx.c | 38 ++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index 0c1cc842cf..2a34465e46 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -941,9 +941,6 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq) desc = &desc_base[q->head_idx]; dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm)); desc->addr = dma_addr; - desc->len = rxq->hdr_seg_size; - desc->opcode = (q->num_segs > 1) ? IONIC_RXQ_DESC_OPCODE_SG : - IONIC_RXQ_DESC_OPCODE_SIMPLE; rxm->next = NULL; prev_rxm_seg = rxm; @@ -963,7 +960,6 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq) data_iova = rte_mbuf_data_iova(rxm_seg); dma_addr = rte_cpu_to_le_64(data_iova); elem->addr = dma_addr; - elem->len = rxq->seg_size; elem++; rxm_seg->next = NULL; @@ -981,6 +977,38 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq) return 0; } +/* + * Perform one-time initialization of descriptor fields + * which will not change for the life of the queue. + */ +static void __rte_cold +ionic_rx_init_descriptors(struct ionic_rx_qcq *rxq) +{ + struct ionic_queue *q = &rxq->qcq.q; + struct ionic_rxq_desc *desc, *desc_base = q->base; + struct ionic_rxq_sg_desc *sg_desc, *sg_desc_base = q->sg_base; + uint32_t i, j; + uint8_t opcode; + + opcode = (q->num_segs > 1) ? + IONIC_RXQ_DESC_OPCODE_SG : IONIC_RXQ_DESC_OPCODE_SIMPLE; + + /* + * NB: Only the first segment needs to leave headroom (hdr_seg_size). + * Later segments (seg_size) do not. + */ + for (i = 0; i < q->num_descs; i++) { + desc = &desc_base[i]; + desc->len = rte_cpu_to_le_16(rxq->hdr_seg_size); + desc->opcode = opcode; + + sg_desc = &sg_desc_base[i]; + for (j = 0; j < q->num_segs - 1u; j++) + sg_desc->elems[j].len = + rte_cpu_to_le_16(rxq->seg_size); + } +} + /* * Start Receive Units for specified queue. */ @@ -1010,6 +1038,8 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs, size %u segs %u", rx_queue_id, q->num_descs, rxq->frame_size, q->num_segs); + ionic_rx_init_descriptors(rxq); + err = ionic_lif_rxq_init(rxq); if (err) return err; -- 2.17.1