From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D307FA0548; Tue, 11 Oct 2022 20:59:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C0EDF42C1F; Tue, 11 Oct 2022 20:57:43 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id AB3D542BB1 for ; Tue, 11 Oct 2022 20:57:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665514650; x=1697050650; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cdQDjcpN4bShHDXHTs9vYJo+zpk2Sskcd/93BZMsqBU=; b=BymTRCNEd8dadn8SFx0QlddG9c4oECOj43oX7QpH0AkEH0vYGFbaDetZ tpDQR0OBESPC+ScCaUMMctJUOxBczNb34fxmPRelP8JLkIWlBCqXVCmSE c+mjX/sshGWjLCWtlnuFrM1Fl/hYs7yJXrRHng/WWP39IknKl7RkuJ42V LQt6Lljq/AfjlVpwPSXZdRsep/arxWwtR7ULQE8+VuPkJtJ38VCxB3bWQ olKbImYAxY/UuE3jwhkyMYZzRjnu6A3dXBL6IxUpIo1N+Azg87UicZnRT oZegPem4b2ZBDLNA9sCtqiDMuIL/pNeD2i8FKFquBEWd/K/5v2Xu/ss8T Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="284981655" X-IronPort-AV: E=Sophos;i="5.95,177,1661842800"; d="scan'208";a="284981655" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 11:57:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="604261577" X-IronPort-AV: E=Sophos;i="5.95,177,1661842800"; d="scan'208";a="604261577" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga006.jf.intel.com with ESMTP; 11 Oct 2022 11:57:29 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 21/30] baseband/acc100: implement configurable queue depth Date: Tue, 11 Oct 2022 19:53:37 -0700 Message-Id: <20221012025346.204394-22-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221012025346.204394-1-hernan.vargas@intel.com> References: <20221012025346.204394-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement new feature to make queue depth configurable based on decode or encode mode. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 38faa49189..936a417c3d 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -768,9 +768,15 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; q->vf_id = (q_idx >> ACC100_VF_ID_SHIFT) & 0x3F; q->aq_id = q_idx & 0xF; - q->aq_depth = (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) ? - (1 << d->acc_conf.q_ul_4g.aq_depth_log2) : - (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + q->aq_depth = 0; + if (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_5g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_5g.aq_depth_log2); q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base, queue_offset(d->pf_device, -- 2.37.1