From: Hernan Vargas <hernan.vargas@intel.com>
To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,
maxime.coquelin@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com,
Hernan Vargas <hernan.vargas@intel.com>
Subject: [PATCH v3 28/30] baseband/acc100: add ring companion address
Date: Tue, 11 Oct 2022 19:53:44 -0700 [thread overview]
Message-ID: <20221012025346.204394-29-hernan.vargas@intel.com> (raw)
In-Reply-To: <20221012025346.204394-1-hernan.vargas@intel.com>
Store the virtual address of companion ring as part of queue
information. Use this address to calculate the op address.
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
drivers/baseband/acc/rte_acc100_pmd.c | 175 +++++++++++++++++---------
1 file changed, 113 insertions(+), 62 deletions(-)
diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
index 23c8e47335..f93fd885a3 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -668,6 +668,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
struct acc_device *d = dev->data->dev_private;
struct acc_queue *q;
int16_t q_idx;
+ int ret;
if (d == NULL) {
rte_bbdev_log(ERR, "Undefined device");
@@ -726,8 +727,8 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
RTE_CACHE_LINE_SIZE, conf->socket);
if (q->lb_in == NULL) {
rte_bbdev_log(ERR, "Failed to allocate lb_in memory");
- rte_free(q);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto free_q;
}
q->lb_in_addr_iova = rte_malloc_virt2iova(q->lb_in);
q->lb_out = rte_zmalloc_socket(dev->device->driver->name,
@@ -735,11 +736,18 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
RTE_CACHE_LINE_SIZE, conf->socket);
if (q->lb_out == NULL) {
rte_bbdev_log(ERR, "Failed to allocate lb_out memory");
- rte_free(q->lb_in);
- rte_free(q);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto free_lb_in;
}
q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out);
+ q->companion_ring_addr = rte_zmalloc_socket(dev->device->driver->name,
+ d->sw_ring_max_depth * sizeof(*q->companion_ring_addr),
+ RTE_CACHE_LINE_SIZE, conf->socket);
+ if (q->companion_ring_addr == NULL) {
+ rte_bbdev_log(ERR, "Failed to allocate companion_ring memory");
+ ret = -ENOMEM;
+ goto free_lb_out;
+ }
/*
* Software queue ring wraps synchronously with the HW when it reaches
@@ -759,10 +767,8 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
q_idx = acc100_find_free_queue_idx(dev, conf);
if (q_idx == -1) {
- rte_free(q->lb_in);
- rte_free(q->lb_out);
- rte_free(q);
- return -1;
+ ret = -EINVAL;
+ goto free_companion_ring_addr;
}
q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF;
@@ -789,6 +795,21 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
dev->data->queues[queue_id].queue_private = q;
return 0;
+
+free_companion_ring_addr:
+ rte_free(q->companion_ring_addr);
+ q->companion_ring_addr = NULL;
+free_lb_out:
+ rte_free(q->lb_out);
+ q->lb_out = NULL;
+free_lb_in:
+ rte_free(q->lb_in);
+ q->lb_in = NULL;
+free_q:
+ rte_free(q);
+ q = NULL;
+
+ return ret;
}
static inline void
@@ -861,6 +882,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id)
/* Mark the Queue as un-assigned */
d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFFFFFFFFFF -
(uint64_t) (1 << q->aq_id));
+ rte_free(q->companion_ring_addr);
rte_free(q->lb_in);
rte_free(q->lb_out);
rte_free(q);
@@ -2431,6 +2453,10 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops,
}
desc->req.op_addr = ops[0];
+ /* Keep track of pointers even when multiplexed in single descriptor */
+ struct acc_ptrs *context_ptrs = q->companion_ring_addr + desc_idx;
+ for (i = 0; i < num; i++)
+ context_ptrs->ptr[i].op_addr = ops[i];
#ifdef RTE_LIBRTE_BBDEV_DEBUG
rte_memdump(stderr, "FCW", &desc->req.fcw_le,
@@ -3804,15 +3830,17 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
/* Dequeue one encode operations from ACC100 device in CB mode */
static inline int
dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
- uint16_t total_dequeued_cbs, uint32_t *aq_dequeued)
+ uint16_t *dequeued_ops, uint32_t *aq_dequeued,
+ uint16_t *dequeued_descs)
{
union acc_dma_desc *desc, atom_desc;
union acc_dma_rsp_desc rsp;
struct rte_bbdev_enc_op *op;
int i;
-
- desc = q->ring_addr + ((q->sw_ring_tail + total_dequeued_cbs)
+ int desc_idx = ((q->sw_ring_tail + *dequeued_descs)
& q->sw_ring_wrap_mask);
+
+ desc = q->ring_addr + desc_idx;
atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc,
__ATOMIC_RELAXED);
@@ -3821,7 +3849,8 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
return -1;
rsp.val = atom_desc.rsp.val;
- rte_bbdev_log_debug("Resp. desc %p: %x", desc, rsp.val);
+ rte_bbdev_log_debug("Resp. desc %p: %x num %d\n",
+ desc, rsp.val, desc->req.numCBs);
/* Dequeue */
op = desc->req.op_addr;
@@ -3842,27 +3871,32 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
desc->rsp.add_info_0 = 0; /*Reserved bits */
desc->rsp.add_info_1 = 0; /*Reserved bits */
- /* Flag that the muxing cause loss of opaque data */
- op->opaque_data = (void *)-1;
- for (i = 0 ; i < desc->req.numCBs; i++)
- ref_op[i] = op;
+ ref_op[0] = op;
+ struct acc_ptrs *context_ptrs = q->companion_ring_addr + desc_idx;
+ for (i = 1 ; i < desc->req.numCBs; i++)
+ ref_op[i] = context_ptrs->ptr[i].op_addr;
- /* One CB (op) was successfully dequeued */
+ /* One op was successfully dequeued */
+ (*dequeued_descs)++;
+ *dequeued_ops += desc->req.numCBs;
return desc->req.numCBs;
}
-/* Dequeue one encode operations from ACC100 device in TB mode */
+/* Dequeue one LDPC encode operations from ACC100 device in TB mode
+ * That operation may cover multiple descriptors
+ */
static inline int
dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
- uint16_t total_dequeued_cbs, uint32_t *aq_dequeued)
+ uint16_t *dequeued_ops, uint32_t *aq_dequeued,
+ uint16_t *dequeued_descs)
{
union acc_dma_desc *desc, *last_desc, atom_desc;
union acc_dma_rsp_desc rsp;
struct rte_bbdev_enc_op *op;
uint8_t i = 0;
- uint16_t current_dequeued_cbs = 0, cbs_in_tb;
+ uint16_t current_dequeued_descs = 0, descs_in_tb;
- desc = q->ring_addr + ((q->sw_ring_tail + total_dequeued_cbs)
+ desc = q->ring_addr + ((q->sw_ring_tail + *dequeued_descs)
& q->sw_ring_wrap_mask);
atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc,
__ATOMIC_RELAXED);
@@ -3872,10 +3906,10 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
return -1;
/* Get number of CBs in dequeued TB */
- cbs_in_tb = desc->req.cbs_in_tb;
+ descs_in_tb = desc->req.cbs_in_tb;
/* Get last CB */
last_desc = q->ring_addr + ((q->sw_ring_tail
- + total_dequeued_cbs + cbs_in_tb - 1)
+ + *dequeued_descs + descs_in_tb - 1)
& q->sw_ring_wrap_mask);
/* Check if last CB in TB is ready to dequeue (and thus
* the whole TB) - checking sdone bit. If not return.
@@ -3891,15 +3925,17 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
/* Clearing status, it will be set based on response */
op->status = 0;
- while (i < cbs_in_tb) {
+ while (i < descs_in_tb) {
desc = q->ring_addr + ((q->sw_ring_tail
- + total_dequeued_cbs)
+ + *dequeued_descs)
& q->sw_ring_wrap_mask);
atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc,
__ATOMIC_RELAXED);
rsp.val = atom_desc.rsp.val;
- rte_bbdev_log_debug("Resp. desc %p: %x", desc,
- rsp.val);
+ rte_bbdev_log_debug("Resp. desc %p: %x descs %d cbs %d\n",
+ desc,
+ rsp.val, descs_in_tb,
+ desc->req.numCBs);
op->status |= ((rsp.input_err)
? (1 << RTE_BBDEV_DATA_ERROR) : 0);
@@ -3913,14 +3949,15 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
desc->rsp.val = ACC_DMA_DESC_TYPE;
desc->rsp.add_info_0 = 0;
desc->rsp.add_info_1 = 0;
- total_dequeued_cbs++;
- current_dequeued_cbs++;
+ (*dequeued_descs)++;
+ current_dequeued_descs++;
i++;
}
*ref_op = op;
- return current_dequeued_cbs;
+ (*dequeued_ops)++;
+ return current_dequeued_descs;
}
/* Dequeue one decode operation from ACC100 device in CB mode */
@@ -4118,12 +4155,11 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data,
struct rte_bbdev_enc_op **ops, uint16_t num)
{
struct acc_queue *q = q_data->queue_private;
- uint16_t dequeue_num;
uint32_t avail = acc_ring_avail_deq(q);
uint32_t aq_dequeued = 0;
- uint16_t i, dequeued_cbs = 0;
- struct rte_bbdev_enc_op *op;
+ uint16_t i, dequeued_ops = 0, dequeued_descs = 0;
int ret;
+ struct rte_bbdev_enc_op *op;
if (avail == 0)
return 0;
#ifdef RTE_LIBRTE_BBDEV_DEBUG
@@ -4132,31 +4168,35 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data,
return 0;
}
#endif
+ op = (q->ring_addr + (q->sw_ring_tail &
+ q->sw_ring_wrap_mask))->req.op_addr;
+ if (unlikely(ops == NULL || op == NULL))
+ return 0;
- dequeue_num = (avail < num) ? avail : num;
+ int cbm = op->turbo_enc.code_block_mode;
- for (i = 0; i < dequeue_num; ++i) {
- op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs)
- & q->sw_ring_wrap_mask))->req.op_addr;
- if (op->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
- ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs,
- &aq_dequeued);
+ for (i = 0; i < num; i++) {
+ if (cbm == RTE_BBDEV_TRANSPORT_BLOCK)
+ ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops],
+ &dequeued_ops, &aq_dequeued,
+ &dequeued_descs);
else
- ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs,
- &aq_dequeued);
-
+ ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops],
+ &dequeued_ops, &aq_dequeued,
+ &dequeued_descs);
if (ret < 0)
break;
- dequeued_cbs += ret;
+ if (dequeued_ops >= num)
+ break;
}
q->aq_dequeued += aq_dequeued;
- q->sw_ring_tail += dequeued_cbs;
+ q->sw_ring_tail += dequeued_descs;
/* Update enqueue stats */
- q_data->queue_stats.dequeued_count += i;
+ q_data->queue_stats.dequeued_count += dequeued_ops;
- return i;
+ return dequeued_ops;
}
/* Dequeue LDPC encode operations from ACC100 device. */
@@ -4167,24 +4207,37 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
struct acc_queue *q = q_data->queue_private;
uint32_t avail = acc_ring_avail_deq(q);
uint32_t aq_dequeued = 0;
- uint16_t dequeue_num, i, dequeued_cbs = 0, dequeued_descs = 0;
+ uint16_t i, dequeued_ops = 0, dequeued_descs = 0;
int ret;
+ struct rte_bbdev_enc_op *op;
+ union acc_dma_desc *desc;
+ if (q == NULL)
+ return 0;
#ifdef RTE_LIBRTE_BBDEV_DEBUG
- if (unlikely(ops == 0 && q == NULL))
+ if (unlikely(ops == 0))
return 0;
#endif
+ desc = q->ring_addr + (q->sw_ring_tail & q->sw_ring_wrap_mask);
+ if (unlikely(desc == NULL))
+ return 0;
+ op = desc->req.op_addr;
+ if (unlikely(ops == NULL || op == NULL))
+ return 0;
+ int cbm = op->ldpc_enc.code_block_mode;
- dequeue_num = RTE_MIN(avail, num);
-
- for (i = 0; i < dequeue_num; i++) {
- ret = dequeue_enc_one_op_cb(q, &ops[dequeued_cbs],
- dequeued_descs, &aq_dequeued);
+ for (i = 0; i < avail; i++) {
+ if (cbm == RTE_BBDEV_TRANSPORT_BLOCK)
+ ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops],
+ &dequeued_ops, &aq_dequeued,
+ &dequeued_descs);
+ else
+ ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops],
+ &dequeued_ops, &aq_dequeued,
+ &dequeued_descs);
if (ret < 0)
break;
- dequeued_cbs += ret;
- dequeued_descs++;
- if (dequeued_cbs >= num)
+ if (dequeued_ops >= num)
break;
}
@@ -4192,12 +4245,10 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
q->sw_ring_tail += dequeued_descs;
/* Update enqueue stats */
- q_data->queue_stats.dequeued_count += dequeued_cbs;
-
- return dequeued_cbs;
+ q_data->queue_stats.dequeued_count += dequeued_ops;
+ return dequeued_ops;
}
-
/* Dequeue decode operations from ACC100 device. */
static uint16_t
acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data,
--
2.37.1
next prev parent reply other threads:[~2022-10-11 19:00 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-12 2:53 [PATCH v3 00/30] baseband/acc100: changes for 22.11 Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 01/30] baseband/acc100: fix ring availability calculation Hernan Vargas
2022-10-14 9:18 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 02/30] baseband/acc100: add function to check AQ availability Hernan Vargas
2022-10-14 9:25 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 03/30] baseband/acc100: memory leak fix Hernan Vargas
2022-10-14 9:29 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 04/30] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-10-14 9:33 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 05/30] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-10-14 9:35 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 06/30] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-10-14 9:39 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 07/30] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-10-14 9:48 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 08/30] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-10-14 9:55 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 09/30] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-10-14 9:56 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 10/30] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-10-14 9:56 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 11/30] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-10-14 10:02 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 12/30] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 13/30] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 14/30] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 15/30] baseband/acc100: add enqueue status Hernan Vargas
2022-10-14 10:04 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 16/30] baseband/acc100: add scatter-gather support Hernan Vargas
2022-10-14 10:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 17/30] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-10-14 10:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 18/30] baseband/acc100: enable input validation by default Hernan Vargas
2022-10-13 12:56 ` [EXT] " Akhil Goyal
2022-10-18 16:28 ` Maxime Coquelin
2022-10-19 22:12 ` Chautru, Nicolas
2022-10-21 8:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 19/30] baseband/acc100: added LDPC transport block support Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 20/30] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 21/30] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 22/30] baseband/acc100: add queue stop operation Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 23/30] baseband/acc100: update uplink CB input length Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 24/30] baseband/acc100: rename ldpc encode function arg Hernan Vargas
2022-10-13 13:04 ` [EXT] " Akhil Goyal
2022-10-12 2:53 ` [PATCH v3 25/30] baseband/acc100: update log messages Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 26/30] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 27/30] baseband/acc100: update device info Hernan Vargas
2022-10-12 2:53 ` Hernan Vargas [this message]
2022-10-12 2:53 ` [PATCH v3 29/30] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-10-13 13:09 ` [EXT] " Akhil Goyal
2022-10-12 2:53 ` [PATCH v3 30/30] baseband/acc100: configure PMON control registers Hernan Vargas
2022-10-13 8:28 ` [EXT] [PATCH v3 00/30] baseband/acc100: changes for 22.11 Akhil Goyal
2022-10-13 13:01 ` Akhil Goyal
2022-10-14 2:46 ` Chautru, Nicolas
2022-10-14 6:33 ` Akhil Goyal
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