From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 335DBA0548; Tue, 11 Oct 2022 21:00:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 626AF42C87; Tue, 11 Oct 2022 20:57:52 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 7C53042BEC for ; Tue, 11 Oct 2022 20:57:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665514654; x=1697050654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3E7Ia2zw4P0zd3AdBSO5vApW0vp4/4uFAtwR2BGNH/E=; b=O7LSsB7wQ5BIM7zQFwJScNadGSkFdzo+U2o4JKj1LaErTAqJJgOg+b84 uOyYEsvFw44CVHYnENVOMLTyB3EdNwlPQILLag5fdcZVve2NbVqh+foMI BxGyZ4Yqt5NrIh9XnD5B/CHQMHOiZKQplvVm+dmBEoYeN8y+5s8vkZpoF KxqPPnKJXUNTkQ/2Sz29NS9uFVfNfN+09wMq8CFNTWFCYgYwndXy3Fugd D5+s9lJDvoaQqThYSobzuOOQABxXpAORX/2mGVDQIDExiUDVcwyZL3Hne ZLLR9r7VpDVfGfg2U74ZCjOmvXNH027qmRrOrYtlngsyMJ09Fu8l98deD g==; X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="284981672" X-IronPort-AV: E=Sophos;i="5.95,177,1661842800"; d="scan'208";a="284981672" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 11:57:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="604261608" X-IronPort-AV: E=Sophos;i="5.95,177,1661842800"; d="scan'208";a="604261608" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga006.jf.intel.com with ESMTP; 11 Oct 2022 11:57:33 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 30/30] baseband/acc100: configure PMON control registers Date: Tue, 11 Oct 2022 19:53:46 -0700 Message-Id: <20221012025346.204394-31-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221012025346.204394-1-hernan.vargas@intel.com> References: <20221012025346.204394-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable performance monitor control registers. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc100_pmd.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index 28063b3db0..ca84ee792a 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -115,6 +115,8 @@ struct acc100_registry_addr { unsigned int depth_log1_offset; unsigned int qman_group_func; unsigned int ddr_range; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; }; /* Structure holding registry addresses for PF */ @@ -144,6 +146,8 @@ static const struct acc100_registry_addr pf_reg_addr = { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; /* Structure holding registry addresses for VF */ -- 2.37.1