From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <jerinj@marvell.com>, <dev@dpdk.org>
Subject: [PATCH v2 07/13] common/cnxk: sync NIX HW info mbox structure with kernel
Date: Thu, 13 Oct 2022 17:11:50 +0530 [thread overview]
Message-ID: <20221013114156.996517-7-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20221013114156.996517-1-ndabilpuram@marvell.com>
From: Satha Rao <skoteshwar@marvell.com>
Sync nix_hw_info structure with kernel.
Maintain default RR_QUANTUM for VF TL2 same as kernel to make
equal distribution among all VFs.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
drivers/common/cnxk/roc_mbox.h | 8 +++++-
drivers/common/cnxk/roc_nix.c | 9 ++++++-
drivers/common/cnxk/roc_nix.h | 1 +
drivers/common/cnxk/roc_nix_tm.c | 4 ---
drivers/common/cnxk/roc_nix_tm_utils.c | 34 +++++++++++++++++++++-----
5 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index a47e6a8f3b..e8d4ae283d 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1215,7 +1215,13 @@ struct nix_inline_ipsec_lf_cfg {
struct nix_hw_info {
struct mbox_msghdr hdr;
uint16_t __io vwqe_delay;
- uint16_t __io rsvd[15];
+ uint16_t __io max_mtu;
+ uint16_t __io min_mtu;
+ uint32_t __io rpm_dwrr_mtu;
+ uint32_t __io sdp_dwrr_mtu;
+ uint32_t __io lbk_dwrr_mtu;
+ uint32_t __io rsvd32[1];
+ uint64_t __io rsvd[15]; /* Add reserved fields for future expansion */
};
struct nix_bandprof_alloc_req {
diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c
index 8fd8ec8461..2a320cc291 100644
--- a/drivers/common/cnxk/roc_nix.c
+++ b/drivers/common/cnxk/roc_nix.c
@@ -303,8 +303,15 @@ roc_nix_get_hw_info(struct roc_nix *roc_nix)
mbox_alloc_msg_nix_get_hw_info(mbox);
rc = mbox_process_msg(mbox, (void *)&hw_info);
- if (rc == 0)
+ if (rc == 0) {
nix->vwqe_interval = hw_info->vwqe_delay;
+ if (nix->lbk_link)
+ roc_nix->dwrr_mtu = hw_info->lbk_dwrr_mtu;
+ else if (nix->sdp_link)
+ roc_nix->dwrr_mtu = hw_info->sdp_dwrr_mtu;
+ else
+ roc_nix->dwrr_mtu = hw_info->rpm_dwrr_mtu;
+ }
return rc;
}
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 34cb2c717c..6636ee52c1 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -426,6 +426,7 @@ struct roc_nix {
uint32_t ipsec_in_min_spi;
uint32_t ipsec_in_max_spi;
uint32_t ipsec_out_max_sa;
+ uint32_t dwrr_mtu;
bool ipsec_out_sso_pffunc;
bool custom_sa_action;
/* End of input parameters */
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 81fa6b1d93..be8da714cd 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -256,10 +256,6 @@ nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)
if (node->weight > roc_nix_tm_max_sched_wt_get())
return NIX_ERR_TM_WEIGHT_EXCEED;
- /* Maintain minimum weight */
- if (!node->weight)
- node->weight = 1;
-
node->hw_lvl = nix_tm_lvl2nix(nix, lvl);
node->rr_prio = 0xF;
node->max_prio = UINT32_MAX;
diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 193f9df5ff..d33e793664 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -644,9 +644,25 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
return k;
}
+static inline int
+nix_tm_default_rr_weight(struct nix *nix)
+{
+ struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix);
+ uint32_t max_pktlen = roc_nix_max_pkt_len(roc_nix);
+ uint32_t weight;
+
+ /* Reduce TX VTAG Insertions */
+ max_pktlen -= 8;
+ weight = max_pktlen / roc_nix->dwrr_mtu;
+ if (max_pktlen % roc_nix->dwrr_mtu)
+ weight += 1;
+
+ return weight;
+}
+
uint8_t
-nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
- volatile uint64_t *reg, volatile uint64_t *regval)
+nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, volatile uint64_t *reg,
+ volatile uint64_t *regval)
{
uint64_t strict_prio = node->priority;
uint32_t hw_lvl = node->hw_lvl;
@@ -654,8 +670,14 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
uint64_t rr_quantum;
uint8_t k = 0;
- /* For CN9K, weight needs to be converted to quantum */
- rr_quantum = nix_tm_weight_to_rr_quantum(node->weight);
+ /* If minimum weight not provided, then by default RR_QUANTUM
+ * should be in sync with kernel, i.e., single MTU value
+ */
+ if (!node->weight)
+ rr_quantum = nix_tm_default_rr_weight(nix);
+ else
+ /* For CN9K, weight needs to be converted to quantum */
+ rr_quantum = nix_tm_weight_to_rr_quantum(node->weight);
/* For children to root, strict prio is default if either
* device root is TL2 or TL1 Static Priority is disabled.
@@ -666,8 +688,8 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, "
"prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)",
- nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id,
- strict_prio, rr_quantum, node);
+ nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, strict_prio,
+ rr_quantum, node);
switch (hw_lvl) {
case NIX_TXSCH_LVL_SMQ:
--
2.25.1
next prev parent reply other threads:[~2022-10-13 11:42 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-11 12:01 [PATCH 01/13] common/cnxk: set MTU size on SDP based on SoC type Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 02/13] common/cnxk: add devargs for soft expiry poll frequency Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 03/13] net/cnxk: fix later skip to include mbuf priv Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 04/13] net/cnxk: add use nixtx offset for cn10kb Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 05/13] common/cnxk: fix RQ mask config for cn10kb chip Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 06/13] common/cnxk: fix schedule weight update Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 07/13] common/cnxk: sync NIX HW info mbox structure with kernel Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 08/13] common/cnxk: revert VF root weight Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 09/13] common/cnxk: set hysteresis bit to one Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 10/13] net/cnxk: handle SA soft packet and byte expiry events Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 11/13] common/cnxk: sync mailbox for channel and bpid map Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 12/13] net/cnxk: remove unnecessary dptr update Nithin Dabilpuram
2022-10-11 12:01 ` [PATCH 13/13] net/cnxk: remove duplicate mempool debug checks Nithin Dabilpuram
2022-10-12 6:53 ` Jerin Jacob
2022-10-13 11:41 ` [PATCH v2 01/13] common/cnxk: set MTU size on SDP based on SoC type Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 02/13] common/cnxk: add devargs for soft expiry poll frequency Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 03/13] net/cnxk: fix later skip to include mbuf priv Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 04/13] net/cnxk: use NIX Tx offset for cn10kb Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 05/13] common/cnxk: fix RQ mask config for cn10kb chip Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 06/13] common/cnxk: fix schedule weight update Nithin Dabilpuram
2022-10-13 11:41 ` Nithin Dabilpuram [this message]
2022-10-13 11:41 ` [PATCH v2 08/13] common/cnxk: set hysteresis bit to one Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 09/13] net/cnxk: handle SA soft packet and byte expiry events Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 10/13] common/cnxk: sync mailbox for channel and bpid map Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 11/13] net/cnxk: remove unnecessary dptr update Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 12/13] net/cnxk: remove duplicate mempool debug checks Nithin Dabilpuram
2022-10-13 11:41 ` [PATCH v2 13/13] net/cnxk: handle hard expiry events Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 01/13] common/cnxk: set MTU size on SDP based on SoC type Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 02/13] common/cnxk: add devargs for soft expiry poll frequency Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 03/13] net/cnxk: fix later skip to include mbuf priv Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 04/13] net/cnxk: use NIX Tx offset for cn10kb Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 05/13] common/cnxk: fix RQ mask config for cn10kb chip Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 06/13] common/cnxk: fix schedule weight update Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 07/13] common/cnxk: sync NIX HW info mbox structure with kernel Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 08/13] common/cnxk: set hysteresis bit to one Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 09/13] net/cnxk: handle SA soft packet and byte expiry events Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 10/13] common/cnxk: sync mailbox for channel and bpid map Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 11/13] net/cnxk: remove unnecessary dptr update Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 12/13] net/cnxk: remove duplicate mempool debug checks Nithin Dabilpuram
2022-10-14 5:43 ` [PATCH v3 13/13] net/cnxk: handle hard expiry events Nithin Dabilpuram
2022-10-18 11:04 ` Jerin Jacob
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221013114156.996517-7-ndabilpuram@marvell.com \
--to=ndabilpuram@marvell.com \
--cc=dev@dpdk.org \
--cc=jerinj@marvell.com \
--cc=kirankumark@marvell.com \
--cc=skori@marvell.com \
--cc=skoteshwar@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).