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Received-SPF: Pass (protection.outlook.com: domain of ddn.com designates 50.222.100.11 as permitted sender) receiver=protection.outlook.com; client-ip=50.222.100.11; helo=uww-mx01.datadirectnet.com; pr=C Received: from uww-mx01.datadirectnet.com (50.222.100.11) by MW2NAM04FT059.mail.protection.outlook.com (10.13.30.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.20 via Frontend Transport; Mon, 17 Oct 2022 15:45:12 +0000 Received: from localhost (unknown [10.68.0.8]) by uww-mx01.datadirectnet.com (Postfix) with ESMTP id 5EA6B20C687A; Mon, 17 Oct 2022 09:46:22 -0600 (MDT) From: Michael Piszczek To: dev@dpdk.org Cc: Michael Piszczek Subject: [PATCH v6] pci: read amd iommu virtual address width Date: Mon, 17 Oct 2022 17:45:06 +0200 Message-Id: <20221017154507.934995-1-mpiszczek@ddn.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220912160157.3642968-2-mpiszczek@ddn.com> References: <20220912160157.3642968-2-mpiszczek@ddn.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW2NAM04FT059:EE_|SA0PR19MB4285:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 8f413ff4-a1b2-4a2b-183d-08dab056941f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: ddn.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2022 15:45:12.4307 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f413ff4-a1b2-4a2b-183d-08dab056941f X-MS-Exchange-CrossTenant-Id: 753b6e26-6fd3-43e6-8248-3f1735d59bb4 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=753b6e26-6fd3-43e6-8248-3f1735d59bb4; Ip=[50.222.100.11]; Helo=[uww-mx01.datadirectnet.com] X-MS-Exchange-CrossTenant-AuthSource: MW2NAM04FT059.eop-NAM04.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR19MB4285 X-Mailman-Approved-At: Mon, 24 Oct 2022 17:33:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add code to read the virtual address width for AMD processors. Updated pci_device_iommu_support_va() to use glob to find iommu capability files. Signed-off-by: Michael Piszczek --- drivers/bus/pci/linux/pci.c | 58 ++++++++++++++++++++++--------------- 1 file changed, 35 insertions(+), 23 deletions(-) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index ebd1395502..291090ba7b 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -480,42 +481,53 @@ rte_pci_scan(void) } #if defined(RTE_ARCH_X86) + bool pci_device_iommu_support_va(const struct rte_pci_device *dev) { -#define VTD_CAP_MGAW_SHIFT 16 -#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) +#define VTD_CAP_MGAW_SHIFT 16 +#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) +#define RD_AMD_CAP_VASIZE_SHIFT 15 +#define RD_AMD_CAP_VASIZE_MASK (0x7F << RD_AMD_CAP_VASIZE_SHIFT) + int rc; const struct rte_pci_addr *addr = &dev->addr; - char filename[PATH_MAX]; - FILE *fp; - uint64_t mgaw, vtd_cap_reg = 0; + char pattern[PATH_MAX]; + glob_t glob_results; + uint64_t mgaw = 0; - snprintf(filename, sizeof(filename), - "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", + snprintf(pattern, sizeof(pattern), + "%s/" PCI_PRI_FMT "/iommu/*-iommu/cap", rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid, addr->function); - fp = fopen(filename, "r"); - if (fp == NULL) { - /* We don't have an Intel IOMMU, assume VA supported */ - if (errno == ENOENT) - return true; + rc = glob(pattern, 0, NULL, &glob_results); + if (rc != 0 && glob_results.gl_pathc == 1) { + const char *filename = glob_results.gl_pathv[0]; + FILE *fp = fopen(filename, "r"); - RTE_LOG(ERR, EAL, "%s(): can't open %s: %s\n", - __func__, filename, strerror(errno)); - return false; - } + if (fp != NULL) { + uint64_t cap_reg = 0; - /* We have an Intel IOMMU */ - if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) { - RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename); - fclose(fp); - return false; + if (fscanf(fp, "%" PRIx64, &cap_reg) != 1) { + RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename); + } + else if (strstr(filename, "intel-iommu") != NULL) { + /* We have an Intel IOMMU */ + mgaw = ((cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1; + } + else if (strstr(filename, "amd-iommu") != NULL) { + /* We have an Amd IOMMU */ + mgaw = ((cap_reg & RD_AMD_CAP_VASIZE_MASK) >> RD_AMD_CAP_VASIZE_SHIFT) + 1; + } + + fclose(fp); + } } - fclose(fp); + globfree(&glob_results); - mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1; + if (mgaw == 0) + return false; /* * Assuming there is no limitation by now. We can not know at this point -- 2.34.1