[PATCH v3 1/2] common/qat: read hw slice configuration

[PATCH v3 1/2] common/qat: read hw slice configuration

[Arek Kusztal]

Read slice configuration of QAT capabilities.
This will allow to recognize if specific hw function
is available on particular device.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
v2:
- added generation specific functions
v3:
- split into two patches
- fixed checkpatch issues

 drivers/common/qat/dev/qat_dev_gen1.c   |  8 ++++++++
 drivers/common/qat/dev/qat_dev_gen2.c   |  8 ++++++++
 drivers/common/qat/dev/qat_dev_gen3.c   | 13 +++++++++++++
 drivers/common/qat/dev/qat_dev_gen4.c   |  8 ++++++++
 drivers/common/qat/qat_adf/icp_qat_hw.h | 18 ++++++++++++++++++
 drivers/common/qat/qat_device.c         | 10 +++++++++-
 drivers/common/qat/qat_device.h         |  8 +++++++-
 7 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c b/drivers/common/qat/dev/qat_dev_gen1.c
index c34ae5a51c..cf480dcba8 100644
--- a/drivers/common/qat/dev/qat_dev_gen1.c
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -241,12 +241,20 @@ qat_dev_get_extra_size_gen1(void)
 	return 0;
 }
 
+static int
+qat_get_dev_slice_map_gen1(uint16_t *map __rte_unused,
+	const struct rte_pci_device *pci_dev __rte_unused)
+{
+	return 0;
+}
+
 static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen1 = {
 	.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
 	.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
 	.qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
 	.qat_dev_read_config = qat_dev_read_config_gen1,
 	.qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+	.qat_dev_get_slice_map = qat_get_dev_slice_map_gen1,
 };
 
 RTE_INIT(qat_dev_gen_gen1_init)
diff --git a/drivers/common/qat/dev/qat_dev_gen2.c b/drivers/common/qat/dev/qat_dev_gen2.c
index f077fe9eef..f51be46eb0 100644
--- a/drivers/common/qat/dev/qat_dev_gen2.c
+++ b/drivers/common/qat/dev/qat_dev_gen2.c
@@ -21,12 +21,20 @@ static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen2 = {
 	.qat_qp_get_hw_data = qat_qp_get_hw_data_gen1,
 };
 
+static int
+qat_dev_get_slice_map_gen2(uint16_t *map __rte_unused,
+	const struct rte_pci_device *pci_dev __rte_unused)
+{
+	return 0;
+}
+
 static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen2 = {
 	.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
 	.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
 	.qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
 	.qat_dev_read_config = qat_dev_read_config_gen1,
 	.qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+	.qat_dev_get_slice_map = qat_dev_get_slice_map_gen2,
 };
 
 RTE_INIT(qat_dev_gen_gen2_init)
diff --git a/drivers/common/qat/dev/qat_dev_gen3.c b/drivers/common/qat/dev/qat_dev_gen3.c
index de3fa17fa9..e4197f3c0f 100644
--- a/drivers/common/qat/dev/qat_dev_gen3.c
+++ b/drivers/common/qat/dev/qat_dev_gen3.c
@@ -67,12 +67,25 @@ static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen3 = {
 	.qat_qp_get_hw_data = qat_qp_get_hw_data_gen3
 };
 
+static int
+qat_dev_get_slice_map_gen3(uint16_t *map,
+	const struct rte_pci_device *pci_dev)
+{
+	if (rte_pci_read_config(pci_dev, map,
+			ADF1_C4XXXIOV_VFLEGFUSES_LEN,
+			ADF_C4XXXIOV_VFLEGFUSES_OFFSET) < 0) {
+		return -1;
+	}
+	return 0;
+}
+
 static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen3 = {
 	.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
 	.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
 	.qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
 	.qat_dev_read_config = qat_dev_read_config_gen1,
 	.qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+	.qat_dev_get_slice_map = qat_dev_get_slice_map_gen3,
 };
 
 RTE_INIT(qat_dev_gen_gen3_init)
diff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c
index 85d6ddfcf4..1b3a5deabf 100644
--- a/drivers/common/qat/dev/qat_dev_gen4.c
+++ b/drivers/common/qat/dev/qat_dev_gen4.c
@@ -283,6 +283,13 @@ qat_dev_get_misc_bar_gen4(struct rte_mem_resource **mem_resource,
 }
 
 static int
+qat_dev_get_slice_map_gen4(uint16_t *map __rte_unused,
+	const struct rte_pci_device *pci_dev __rte_unused)
+{
+	return 0;
+}
+
+static int
 qat_dev_get_extra_size_gen4(void)
 {
 	return sizeof(struct qat_dev_gen4_extra);
@@ -294,6 +301,7 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen4 = {
 	.qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen4,
 	.qat_dev_read_config = qat_dev_read_config_gen4,
 	.qat_dev_get_extra_size = qat_dev_get_extra_size_gen4,
+	.qat_dev_get_slice_map = qat_dev_get_slice_map_gen4,
 };
 
 RTE_INIT(qat_dev_gen_4_init)
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index e2da701f37..5c420494ac 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -4,6 +4,24 @@
 #ifndef _ICP_QAT_HW_H_
 #define _ICP_QAT_HW_H_
 
+#define ADF_C4XXXIOV_VFLEGFUSES_OFFSET	0x4C
+#define ADF1_C4XXXIOV_VFLEGFUSES_LEN	4
+
+enum icp_qat_slice_mask {
+	ICP_ACCEL_MASK_CIPHER_SLICE = 0x01,
+	ICP_ACCEL_MASK_AUTH_SLICE = 0x02,
+	ICP_ACCEL_MASK_PKE_SLICE = 0x04,
+	ICP_ACCEL_MASK_COMPRESS_SLICE = 0x08,
+	ICP_ACCEL_MASK_DEPRECATED = 0x10,
+	ICP_ACCEL_MASK_EIA3_SLICE = 0x20,
+	ICP_ACCEL_MASK_SHA3_SLICE = 0x40,
+	ICP_ACCEL_MASK_CRYPTO0_SLICE = 0x80,
+	ICP_ACCEL_MASK_CRYPTO1_SLICE = 0x100,
+	ICP_ACCEL_MASK_CRYPTO2_SLICE = 0x200,
+	ICP_ACCEL_MASK_SM3_SLICE = 0x400,
+	ICP_ACCEL_MASK_SM4_SLICE = 0x800
+};
+
 enum icp_qat_hw_ae_id {
 	ICP_QAT_HW_AE_0 = 0,
 	ICP_QAT_HW_AE_1 = 1,
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 30e5cdb573..8ddba0c903 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -361,6 +361,7 @@ static int qat_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 {
 	int sym_ret = 0, asym_ret = 0, comp_ret = 0;
 	int num_pmds_created = 0;
+	uint16_t capa;
 	struct qat_pci_device *qat_pci_dev;
 	struct qat_dev_hw_spec_funcs *ops_hw;
 	struct qat_dev_cmd_param qat_dev_cmd_param[] = {
@@ -368,6 +369,7 @@ static int qat_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 			{ SYM_ENQ_THRESHOLD_NAME, 0 },
 			{ ASYM_ENQ_THRESHOLD_NAME, 0 },
 			{ COMP_ENQ_THRESHOLD_NAME, 0 },
+			[QAT_CMD_SLICE_MAP_POS] = { QAT_CMD_SLICE_MAP, 0},
 			{ NULL, 0 },
 	};
 
@@ -390,10 +392,16 @@ static int qat_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		return -ENODEV;
 	}
 
+	if (ops_hw->qat_dev_get_slice_map(&capa, pci_dev) < 0) {
+		RTE_LOG(ERR, EAL,
+			"Cannot read slice configuration\n");
+		return -1;
+	}
+	qat_dev_cmd_param[QAT_CMD_SLICE_MAP_POS].val = capa;
+
 	sym_ret = qat_sym_dev_create(qat_pci_dev, qat_dev_cmd_param);
 	if (sym_ret == 0) {
 		num_pmds_created++;
-
 	}
 	else
 		QAT_LOG(WARNING,
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index d1512f3b89..3ffd6b2d07 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -8,8 +8,9 @@
 
 #include "qat_common.h"
 #include "qat_logs.h"
-#include "adf_transport_access_macros.h"
 #include "qat_qp.h"
+#include "adf_transport_access_macros.h"
+#include "icp_qat_hw.h"
 
 #define QAT_DETACHED  (0)
 #define QAT_ATTACHED  (1)
@@ -20,6 +21,8 @@
 #define SYM_ENQ_THRESHOLD_NAME "qat_sym_enq_threshold"
 #define ASYM_ENQ_THRESHOLD_NAME "qat_asym_enq_threshold"
 #define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
+#define QAT_CMD_SLICE_MAP "qat_cmd_slice_disable"
+#define QAT_CMD_SLICE_MAP_POS	4
 #define MAX_QP_THRESHOLD_SIZE	32
 
 /**
@@ -34,6 +37,8 @@ typedef int (*qat_dev_get_misc_bar_t)
 typedef int (*qat_dev_read_config_t)
 		(struct qat_pci_device *);
 typedef int (*qat_dev_get_extra_size_t)(void);
+typedef int (*qat_dev_get_slice_map_t)(uint16_t *map,
+		const struct rte_pci_device *pci_dev);
 
 struct qat_dev_hw_spec_funcs {
 	qat_dev_reset_ring_pairs_t	qat_dev_reset_ring_pairs;
@@ -41,6 +46,7 @@ struct qat_dev_hw_spec_funcs {
 	qat_dev_get_misc_bar_t		qat_dev_get_misc_bar;
 	qat_dev_read_config_t		qat_dev_read_config;
 	qat_dev_get_extra_size_t	qat_dev_get_extra_size;
+	qat_dev_get_slice_map_t		qat_dev_get_slice_map;
 };
 
 extern struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[];
-- 
2.13.6

[PATCH v3 2/2] crypto/qat: read hw slice configuration

[Arek Kusztal]

Read slice configuration of QAT capabilities.
This will allow to recognize if specific hw function
is available on particular device.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
v2:
- added generation specific functions
v3:
- split into two patches
- fixed checkpatch issues

 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   | 42 ++++++++++++---
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 41 +++++++++++---
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 80 +++++++++++++++++++++++++---
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 41 +++++++++++---
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  5 +-
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c    | 41 +++++++++++---
 drivers/crypto/qat/qat_asym.c                | 49 ++++++++---------
 drivers/crypto/qat/qat_crypto.h              |  4 +-
 drivers/crypto/qat/qat_sym.c                 | 38 +++++--------
 9 files changed, 254 insertions(+), 87 deletions(-)

diff --git a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
index 4499fdaf2d..67b1892c32 100644
--- a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
+++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
@@ -41,14 +41,42 @@ static struct rte_cryptodev_capabilities qat_asym_crypto_caps_gen1[] = {
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-
-struct qat_capabilities_info
-qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)
+int
+qat_asym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,
+			const char *capa_memz_name,
+			const uint16_t __rte_unused slice_map)
 {
-	struct qat_capabilities_info capa_info;
-	capa_info.data = qat_asym_crypto_caps_gen1;
-	capa_info.size = sizeof(qat_asym_crypto_caps_gen1);
-	return capa_info;
+	const uint32_t size = sizeof(qat_asym_crypto_caps_gen1);
+	uint32_t i;
+
+	internals->capa_mz = rte_memzone_lookup(capa_memz_name);
+	if (internals->capa_mz == NULL) {
+		internals->capa_mz = rte_memzone_reserve(capa_memz_name,
+				size, rte_socket_id(), 0);
+		if (internals->capa_mz == NULL) {
+			QAT_LOG(DEBUG,
+				"Error allocating memzone for capabilities");
+			return -1;
+		}
+	}
+
+	struct rte_cryptodev_capabilities *addr =
+			(struct rte_cryptodev_capabilities *)
+				internals->capa_mz->addr;
+	const struct rte_cryptodev_capabilities *capabilities =
+		qat_asym_crypto_caps_gen1;
+	const uint32_t capa_num =
+		size / sizeof(struct rte_cryptodev_capabilities);
+	uint32_t curr_capa = 0;
+
+	for (i = 0; i < capa_num; i++) {
+		memcpy(addr + curr_capa, capabilities + i,
+			sizeof(struct rte_cryptodev_capabilities));
+		curr_capa++;
+	}
+	internals->qat_dev_capabilities = internals->capa_mz->addr;
+
+	return 0;
 }
 
 uint64_t
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
index 0c64c1e43f..3d01fa7770 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
@@ -275,13 +275,42 @@ struct rte_cryptodev_ops qat_sym_crypto_ops_gen2 = {
 	.sym_configure_raw_dp_ctx = qat_sym_configure_dp_ctx,
 };
 
-static struct qat_capabilities_info
-qat_sym_crypto_cap_get_gen2(struct qat_pci_device *qat_dev __rte_unused)
+static int
+qat_sym_crypto_cap_get_gen2(struct qat_cryptodev_private *internals,
+			const char *capa_memz_name,
+			const uint16_t __rte_unused slice_map)
 {
-	struct qat_capabilities_info capa_info;
-	capa_info.data = qat_sym_crypto_caps_gen2;
-	capa_info.size = sizeof(qat_sym_crypto_caps_gen2);
-	return capa_info;
+	const uint32_t size = sizeof(qat_sym_crypto_caps_gen2);
+	uint32_t i;
+
+	internals->capa_mz = rte_memzone_lookup(capa_memz_name);
+	if (internals->capa_mz == NULL) {
+		internals->capa_mz = rte_memzone_reserve(capa_memz_name,
+				size, rte_socket_id(), 0);
+		if (internals->capa_mz == NULL) {
+			QAT_LOG(DEBUG,
+				"Error allocating memzone for capabilities");
+			return -1;
+		}
+	}
+
+	struct rte_cryptodev_capabilities *addr =
+			(struct rte_cryptodev_capabilities *)
+				internals->capa_mz->addr;
+	const struct rte_cryptodev_capabilities *capabilities =
+		qat_sym_crypto_caps_gen2;
+	const uint32_t capa_num =
+		size / sizeof(struct rte_cryptodev_capabilities);
+	uint32_t curr_capa = 0;
+
+	for (i = 0; i < capa_num; i++) {
+		memcpy(addr + curr_capa, capabilities + i,
+			sizeof(struct rte_cryptodev_capabilities));
+		curr_capa++;
+	}
+	internals->qat_dev_capabilities = internals->capa_mz->addr;
+
+	return 0;
 }
 
 RTE_INIT(qat_sym_crypto_gen2_init)
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index d1285cdbd4..7f00f6097d 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -143,13 +143,81 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = {
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-static struct qat_capabilities_info
-qat_sym_crypto_cap_get_gen3(struct qat_pci_device *qat_dev __rte_unused)
+static int
+check_cipher_capa(const struct rte_cryptodev_capabilities *cap,
+		enum rte_crypto_cipher_algorithm algo)
+{
+	if (cap->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
+		return 0;
+	if (cap->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
+		return 0;
+	if (cap->sym.cipher.algo != algo)
+		return 0;
+	return 1;
+}
+
+static int
+check_auth_capa(const struct rte_cryptodev_capabilities *cap,
+		enum rte_crypto_auth_algorithm algo)
 {
-	struct qat_capabilities_info capa_info;
-	capa_info.data = qat_sym_crypto_caps_gen3;
-	capa_info.size = sizeof(qat_sym_crypto_caps_gen3);
-	return capa_info;
+	if (cap->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
+		return 0;
+	if (cap->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		return 0;
+	if (cap->sym.auth.algo != algo)
+		return 0;
+	return 1;
+}
+
+static int
+qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,
+			const char *capa_memz_name, const uint16_t slice_map)
+{
+	const uint32_t size = sizeof(qat_sym_crypto_caps_gen3);
+	uint32_t i;
+
+	internals->capa_mz = rte_memzone_lookup(capa_memz_name);
+	if (internals->capa_mz == NULL) {
+		internals->capa_mz = rte_memzone_reserve(capa_memz_name,
+				size, rte_socket_id(), 0);
+		if (internals->capa_mz == NULL) {
+			QAT_LOG(DEBUG,
+				"Error allocating memzone for capabilities");
+			return -1;
+		}
+	}
+
+	struct rte_cryptodev_capabilities *addr =
+			(struct rte_cryptodev_capabilities *)
+				internals->capa_mz->addr;
+	const struct rte_cryptodev_capabilities *capabilities =
+		qat_sym_crypto_caps_gen3;
+	const uint32_t capa_num =
+		size / sizeof(struct rte_cryptodev_capabilities);
+	uint32_t curr_capa = 0;
+
+	for (i = 0; i < capa_num; i++) {
+		if (slice_map & ICP_ACCEL_MASK_SM4_SLICE && (
+			check_cipher_capa(&capabilities[i],
+				RTE_CRYPTO_CIPHER_SM4_ECB) ||
+			check_cipher_capa(&capabilities[i],
+				RTE_CRYPTO_CIPHER_SM4_CBC) ||
+			check_cipher_capa(&capabilities[i],
+				RTE_CRYPTO_CIPHER_SM4_CTR))) {
+			continue;
+		}
+		if (slice_map & ICP_ACCEL_MASK_SM3_SLICE && (
+			check_auth_capa(&capabilities[i],
+				RTE_CRYPTO_AUTH_SM3))) {
+			continue;
+		}
+		memcpy(addr + curr_capa, capabilities + i,
+			sizeof(struct rte_cryptodev_capabilities));
+		curr_capa++;
+	}
+	internals->qat_dev_capabilities = internals->capa_mz->addr;
+
+	return 0;
 }
 
 static __rte_always_inline void
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
index efbbbda4b6..b1e5fa9a82 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
@@ -103,13 +103,42 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = {
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-static struct qat_capabilities_info
-qat_sym_crypto_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused)
+static int
+qat_sym_crypto_cap_get_gen4(struct qat_cryptodev_private *internals,
+			const char *capa_memz_name,
+			const uint16_t __rte_unused slice_map)
 {
-	struct qat_capabilities_info capa_info;
-	capa_info.data = qat_sym_crypto_caps_gen4;
-	capa_info.size = sizeof(qat_sym_crypto_caps_gen4);
-	return capa_info;
+	const uint32_t size = sizeof(qat_sym_crypto_caps_gen4);
+	uint32_t i;
+
+	internals->capa_mz = rte_memzone_lookup(capa_memz_name);
+	if (internals->capa_mz == NULL) {
+		internals->capa_mz = rte_memzone_reserve(capa_memz_name,
+				size, rte_socket_id(), 0);
+		if (internals->capa_mz == NULL) {
+			QAT_LOG(DEBUG,
+				"Error allocating memzone for capabilities");
+			return -1;
+		}
+	}
+
+	struct rte_cryptodev_capabilities *addr =
+			(struct rte_cryptodev_capabilities *)
+				internals->capa_mz->addr;
+	const struct rte_cryptodev_capabilities *capabilities =
+		qat_sym_crypto_caps_gen4;
+	const uint32_t capa_num =
+		size / sizeof(struct rte_cryptodev_capabilities);
+	uint32_t curr_capa = 0;
+
+	for (i = 0; i < capa_num; i++) {
+		memcpy(addr + curr_capa, capabilities + i,
+			sizeof(struct rte_cryptodev_capabilities));
+		curr_capa++;
+	}
+	internals->qat_dev_capabilities = internals->capa_mz->addr;
+
+	return 0;
 }
 
 static __rte_always_inline void
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
index 9e01755fd9..524c291340 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
@@ -928,8 +928,9 @@ void
 qat_sym_session_set_ext_hash_flags_gen2(struct qat_sym_session *session,
 		uint8_t hash_flag);
 
-struct qat_capabilities_info
-qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev);
+int
+qat_asym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,
+			const char *capa_memz_name, const uint16_t slice_map);
 
 uint64_t
 qat_asym_crypto_feature_flags_get_gen1(struct qat_pci_device *qat_dev);
diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
index 462c1a722f..91d5cfa71d 100644
--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
@@ -152,13 +152,42 @@ struct rte_cryptodev_ops qat_sym_crypto_ops_gen1 = {
 	.sym_configure_raw_dp_ctx = qat_sym_configure_dp_ctx,
 };
 
-static struct qat_capabilities_info
-qat_sym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)
+static int
+qat_sym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,
+			const char *capa_memz_name,
+			const uint16_t __rte_unused slice_map)
 {
-	struct qat_capabilities_info capa_info;
-	capa_info.data = qat_sym_crypto_caps_gen1;
-	capa_info.size = sizeof(qat_sym_crypto_caps_gen1);
-	return capa_info;
+	const uint32_t size = sizeof(qat_sym_crypto_caps_gen1);
+	uint32_t i;
+
+	internals->capa_mz = rte_memzone_lookup(capa_memz_name);
+	if (internals->capa_mz == NULL) {
+		internals->capa_mz = rte_memzone_reserve(capa_memz_name,
+				size, rte_socket_id(), 0);
+		if (internals->capa_mz == NULL) {
+			QAT_LOG(DEBUG,
+				"Error allocating memzone for capabilities");
+			return -1;
+		}
+	}
+
+	struct rte_cryptodev_capabilities *addr =
+			(struct rte_cryptodev_capabilities *)
+				internals->capa_mz->addr;
+	const struct rte_cryptodev_capabilities *capabilities =
+		qat_sym_crypto_caps_gen1;
+	const uint32_t capa_num =
+		size / sizeof(struct rte_cryptodev_capabilities);
+	uint32_t curr_capa = 0;
+
+	for (i = 0; i < capa_num; i++) {
+		memcpy(addr + curr_capa, capabilities + i,
+			sizeof(struct rte_cryptodev_capabilities));
+		curr_capa++;
+	}
+	internals->qat_dev_capabilities = internals->capa_mz->addr;
+
+	return 0;
 }
 
 uint64_t
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 19931791c4..b119fcc711 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -1279,14 +1279,12 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,
 		.socket_id = qat_dev_instance->pci_dev->device.numa_node,
 		.private_data_size = sizeof(struct qat_cryptodev_private)
 	};
-	struct qat_capabilities_info capa_info;
-	const struct rte_cryptodev_capabilities *capabilities;
 	const struct qat_crypto_gen_dev_ops *gen_dev_ops =
 		&qat_asym_gen_dev_ops[qat_pci_dev->qat_dev_gen];
 	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
 	char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];
-	uint64_t capa_size;
 	int i = 0;
+	uint16_t slice_map = 0;
 
 	snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
 			qat_pci_dev->name, "asym");
@@ -1343,38 +1341,37 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,
 	internals->qat_dev = qat_pci_dev;
 	internals->dev_id = cryptodev->data->dev_id;
 
-	capa_info = gen_dev_ops->get_capabilities(qat_pci_dev);
-	capabilities = capa_info.data;
-	capa_size = capa_info.size;
-
-	internals->capa_mz = rte_memzone_lookup(capa_memz_name);
-	if (internals->capa_mz == NULL) {
-		internals->capa_mz = rte_memzone_reserve(capa_memz_name,
-				capa_size, rte_socket_id(), 0);
-		if (internals->capa_mz == NULL) {
-			QAT_LOG(DEBUG,
-				"Error allocating memzone for capabilities, "
-				"destroying PMD for %s",
-				name);
-			rte_cryptodev_pmd_destroy(cryptodev);
-			memset(&qat_dev_instance->asym_rte_dev, 0,
-				sizeof(qat_dev_instance->asym_rte_dev));
-			return -EFAULT;
-		}
-	}
-
-	memcpy(internals->capa_mz->addr, capabilities, capa_size);
-	internals->qat_dev_capabilities = internals->capa_mz->addr;
-
 	while (1) {
 		if (qat_dev_cmd_param[i].name == NULL)
 			break;
 		if (!strcmp(qat_dev_cmd_param[i].name, ASYM_ENQ_THRESHOLD_NAME))
 			internals->min_enq_burst_threshold =
 					qat_dev_cmd_param[i].val;
+		if (!strcmp(qat_dev_cmd_param[i].name, QAT_CMD_SLICE_MAP))
+			slice_map = qat_dev_cmd_param[i].val;
 		i++;
 	}
 
+	if (slice_map & ICP_ACCEL_MASK_PKE_SLICE) {
+		QAT_LOG(ERR, "Device %s does not support PKE slice",
+				name);
+		rte_cryptodev_pmd_destroy(cryptodev);
+		memset(&qat_dev_instance->asym_rte_dev, 0,
+			sizeof(qat_dev_instance->asym_rte_dev));
+		return -1;
+	}
+
+	if (gen_dev_ops->get_capabilities(internals,
+			capa_memz_name, slice_map) < 0) {
+		QAT_LOG(ERR,
+			"Device cannot obtain capabilities, destroying PMD for %s",
+			name);
+		rte_cryptodev_pmd_destroy(cryptodev);
+		memset(&qat_dev_instance->asym_rte_dev, 0,
+			sizeof(qat_dev_instance->asym_rte_dev));
+		return -1;
+	}
+
 	qat_pci_dev->asym_dev = internals;
 	internals->service_type = QAT_SERVICE_ASYMMETRIC;
 	QAT_LOG(DEBUG, "Created QAT ASYM device %s as cryptodev instance %d",
diff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h
index cf386d0ed0..6fe1326c51 100644
--- a/drivers/crypto/qat/qat_crypto.h
+++ b/drivers/crypto/qat/qat_crypto.h
@@ -44,8 +44,8 @@ struct qat_capabilities_info {
 	uint64_t size;
 };
 
-typedef struct qat_capabilities_info (*get_capabilities_info_t)
-			(struct qat_pci_device *qat_dev);
+typedef int (*get_capabilities_info_t)(struct qat_cryptodev_private *internals,
+			const char *capa_memz_name, uint16_t slice_map);
 
 typedef uint64_t (*get_feature_flags_t)(struct qat_pci_device *qat_dev);
 
diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index 54c3d59a51..018dff2296 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -182,6 +182,7 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
 		struct qat_dev_cmd_param *qat_dev_cmd_param __rte_unused)
 {
 	int i = 0, ret = 0;
+	uint16_t slice_map = 0;
 	struct qat_device_info *qat_dev_instance =
 			&qat_pci_devs[qat_pci_dev->qat_dev_id];
 	struct rte_cryptodev_pmd_init_params init_params = {
@@ -193,11 +194,8 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
 	char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];
 	struct rte_cryptodev *cryptodev;
 	struct qat_cryptodev_private *internals;
-	struct qat_capabilities_info capa_info;
-	const struct rte_cryptodev_capabilities *capabilities;
 	const struct qat_crypto_gen_dev_ops *gen_dev_ops =
 		&qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen];
-	uint64_t capa_size;
 
 	snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
 			qat_pci_dev->name, "sym");
@@ -277,37 +275,25 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
 
 	internals->dev_id = cryptodev->data->dev_id;
 
-	capa_info = gen_dev_ops->get_capabilities(qat_pci_dev);
-	capabilities = capa_info.data;
-	capa_size = capa_info.size;
-
-	internals->capa_mz = rte_memzone_lookup(capa_memz_name);
-	if (internals->capa_mz == NULL) {
-		internals->capa_mz = rte_memzone_reserve(capa_memz_name,
-				capa_size, rte_socket_id(), 0);
-		if (internals->capa_mz == NULL) {
-			QAT_LOG(DEBUG,
-				"Error allocating memzone for capabilities, "
-				"destroying PMD for %s", name);
-			ret = -EFAULT;
-			goto error;
-		}
-	}
-
-	memcpy(internals->capa_mz->addr, capabilities, capa_size);
-	internals->qat_dev_capabilities = internals->capa_mz->addr;
-
-	while (1) {
-		if (qat_dev_cmd_param[i].name == NULL)
-			break;
+	while (qat_dev_cmd_param[i].name != NULL) {
 		if (!strcmp(qat_dev_cmd_param[i].name, SYM_ENQ_THRESHOLD_NAME))
 			internals->min_enq_burst_threshold =
 					qat_dev_cmd_param[i].val;
 		if (!strcmp(qat_dev_cmd_param[i].name, QAT_IPSEC_MB_LIB))
 			qat_ipsec_mb_lib = qat_dev_cmd_param[i].val;
+		if (!strcmp(qat_dev_cmd_param[i].name, QAT_CMD_SLICE_MAP))
+			slice_map = qat_dev_cmd_param[i].val;
 		i++;
 	}
 
+	if (gen_dev_ops->get_capabilities(internals,
+			capa_memz_name, slice_map) < 0) {
+		QAT_LOG(ERR,
+			"Device cannot obtain capabilities, destroying PMD for %s",
+			name);
+		ret = -1;
+		goto error;
+	}
 	internals->service_type = QAT_SERVICE_SYMMETRIC;
 	qat_pci_dev->sym_dev = internals;
 	QAT_LOG(DEBUG, "Created QAT SYM device %s as cryptodev instance %d",
-- 
2.13.6

RE: [PATCH v3 1/2] common/qat: read hw slice configuration

[Ji, Kai]

Acked-by: Kai Ji <kai.ji@intel.com>

> -----Original Message-----
> From: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>
> Sent: Tuesday, October 18, 2022 3:02 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Ji, Kai <kai.ji@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH v3 1/2] common/qat: read hw slice configuration
> 
> Read slice configuration of QAT capabilities.
> This will allow to recognize if specific hw function is available on particular
> device.
> 
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
> ---
> v2:
> - added generation specific functions
> v3:
> - split into two patches
> - fixed checkpatch issues
> 
>  drivers/common/qat/dev/qat_dev_gen1.c   |  8 ++++++++
>  drivers/common/qat/dev/qat_dev_gen2.c   |  8 ++++++++
>  drivers/common/qat/dev/qat_dev_gen3.c   | 13 +++++++++++++
>  drivers/common/qat/dev/qat_dev_gen4.c   |  8 ++++++++
>  drivers/common/qat/qat_adf/icp_qat_hw.h | 18 ++++++++++++++++++
>  drivers/common/qat/qat_device.c         | 10 +++++++++-
>  drivers/common/qat/qat_device.h         |  8 +++++++-
>  7 files changed, 71 insertions(+), 2 deletions(-)
> 

RE: [PATCH v3 2/2] crypto/qat: read hw slice configuration

[Ji, Kai]

Acked-by: Kai Ji <kai.ji@intel.com>

> -----Original Message-----
> From: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>
> Sent: Tuesday, October 18, 2022 3:02 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Ji, Kai <kai.ji@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH v3 2/2] crypto/qat: read hw slice configuration
> 
> Read slice configuration of QAT capabilities.
> This will allow to recognize if specific hw function is available on particular
> device.
> 
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
> ---
> v2:
> - added generation specific functions
> v3:
> - split into two patches
> - fixed checkpatch issues
> 
>  drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   | 42 ++++++++++++---
>  drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 41 +++++++++++---
> drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 80
> +++++++++++++++++++++++++---
> drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 41 +++++++++++---
> drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  5 +-
>  drivers/crypto/qat/dev/qat_sym_pmd_gen1.c    | 41 +++++++++++---
>  drivers/crypto/qat/qat_asym.c                | 49 ++++++++---------
>  drivers/crypto/qat/qat_crypto.h              |  4 +-
>  drivers/crypto/qat/qat_sym.c                 | 38 +++++--------
>  9 files changed, 254 insertions(+), 87 deletions(-)
> 

RE: [PATCH v3 1/2] common/qat: read hw slice configuration

[Akhil Goyal]

> Acked-by: Kai Ji <kai.ji@intel.com>
> > Subject: [PATCH v3 1/2] common/qat: read hw slice configuration
> >
> > Read slice configuration of QAT capabilities.
> > This will allow to recognize if specific hw function is available on particular
> > device.
> >
> > Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Series applied to dpdk-next-crypto

Thanks.