From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 92780A0560; Tue, 18 Oct 2022 18:44:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA65642B7D; Tue, 18 Oct 2022 18:43:11 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id A1A2A42829 for ; Tue, 18 Oct 2022 18:42:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111378; x=1697647378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vx3mMM5n3WyzFyLFegciQ/ibPW0GfX/YeMCAlQTTZf8=; b=PKawweFgp7VZ8VrJX/UBe8+TTfv5HpH9Ecf1LFxEuwr4eRgKhkvZW5AD ei85STpIuJxdkFV5HcbiMIPKorcda5YDnSLFATCs82t/3ambLH+/vteAk AQWP+zylApjCUQZjZ5GIxxqJHruComhPWceM4fY4taPVJ3lf63Jw+sCgb LFQDnKTF2h2QZcr94JlyNeU/pTSBo/Jaunk7mRvR6SaorDfUew0PssV5a QqV26+mw62huNmykVcu5uMNYaY5KN6f90i1UNXXTXfsVwS171i9XL9xns 52BeHig3p1XkSc/I56SpZ6Nkdz4G/iGU/sDYHSZOJeULvNeN8bdxUxkLb Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192115" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192115" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836120" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836120" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:57 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 21/30] baseband/acc100: implement configurable queue depth Date: Tue, 18 Oct 2022 17:39:09 -0700 Message-Id: <20221019003918.257506-22-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement new feature to make queue depth configurable based on decode or encode mode. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 94863d7afd..a734be8553 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -776,9 +776,15 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; q->vf_id = (q_idx >> ACC100_VF_ID_SHIFT) & 0x3F; q->aq_id = q_idx & 0xF; - q->aq_depth = (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) ? - (1 << d->acc_conf.q_ul_4g.aq_depth_log2) : - (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + q->aq_depth = 0; + if (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_5g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_5g.aq_depth_log2); q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base, queue_offset(d->pf_device, -- 2.37.1