From: Hernan Vargas <hernan.vargas@intel.com>
To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,
maxime.coquelin@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com,
Hernan Vargas <hernan.vargas@intel.com>,
stable@dpdk.org
Subject: [PATCH v4 02/30] baseband/acc100: add function to check AQ availability
Date: Tue, 18 Oct 2022 17:38:50 -0700 [thread overview]
Message-ID: <20221019003918.257506-3-hernan.vargas@intel.com> (raw)
In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com>
It is possible for some corner case to run more batch enqueue than
supported. A protection is required to avoid that corner case.
Enhance all ACC100 enqueue operations with check to see if there is room
in the atomic queue for enqueueing batches into the queue manager
Check room in AQ for the enqueues batches into Qmgr
Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
drivers/baseband/acc/rte_acc100_pmd.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
index 3b0c8e41dc..7fec2283eb 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -2983,7 +2983,8 @@ static uint16_t
acc100_enqueue_enc(struct rte_bbdev_queue_data *q_data,
struct rte_bbdev_enc_op **ops, uint16_t num)
{
- if (unlikely(num == 0))
+ int32_t aq_avail = acc_aq_avail(q_data, num);
+ if (unlikely((aq_avail <= 0) || (num == 0)))
return 0;
if (ops[0]->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
return acc100_enqueue_enc_tb(q_data, ops, num);
@@ -2996,7 +2997,8 @@ static uint16_t
acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
struct rte_bbdev_enc_op **ops, uint16_t num)
{
- if (unlikely(num == 0))
+ int32_t aq_avail = acc_aq_avail(q_data, num);
+ if (unlikely((aq_avail <= 0) || (num == 0)))
return 0;
if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
return acc100_enqueue_enc_tb(q_data, ops, num);
@@ -3164,8 +3166,11 @@ static uint16_t
acc100_enqueue_dec(struct rte_bbdev_queue_data *q_data,
struct rte_bbdev_dec_op **ops, uint16_t num)
{
- if (unlikely(num == 0))
+ int32_t aq_avail = acc_aq_avail(q_data, num);
+
+ if (unlikely((aq_avail <= 0) || (num == 0)))
return 0;
+
if (ops[0]->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
return acc100_enqueue_dec_tb(q_data, ops, num);
else
@@ -3177,11 +3182,9 @@ static uint16_t
acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
struct rte_bbdev_dec_op **ops, uint16_t num)
{
- struct acc_queue *q = q_data->queue_private;
- int32_t aq_avail = q->aq_depth +
- (q->aq_dequeued - q->aq_enqueued) / 128;
+ int32_t aq_avail = acc_aq_avail(q_data, num);
- if (unlikely((aq_avail == 0) || (num == 0)))
+ if (unlikely((aq_avail <= 0) || (num == 0)))
return 0;
if (ops[0]->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
@@ -3190,7 +3193,6 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
return acc100_enqueue_ldpc_dec_cb(q_data, ops, num);
}
-
/* Dequeue one encode operations from ACC100 device in CB mode */
static inline int
dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
--
2.37.1
next prev parent reply other threads:[~2022-10-18 16:42 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 0:38 [PATCH v4 00/30] baseband/acc100: changes for 22.11 Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 01/30] baseband/acc100: fix ring availability calculation Hernan Vargas
2022-10-19 0:38 ` Hernan Vargas [this message]
2022-10-19 0:38 ` [PATCH v4 03/30] baseband/acc100: memory leak fix Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 04/30] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-10-20 9:58 ` [EXT] " Akhil Goyal
2022-10-19 0:38 ` [PATCH v4 05/30] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 06/30] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 07/30] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 08/30] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 09/30] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 10/30] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-10-19 0:38 ` [PATCH v4 11/30] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 12/30] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 13/30] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 14/30] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 15/30] baseband/acc100: add enqueue status Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 16/30] baseband/acc100: add scatter-gather support Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 17/30] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 18/30] baseband/acc100: enable input validation by default Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 19/30] baseband/acc100: added LDPC transport block support Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 20/30] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 21/30] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 22/30] baseband/acc100: add queue stop operation Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 23/30] baseband/acc100: update uplink CB input length Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 24/30] baseband/acc100: update log messages Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 25/30] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 26/30] baseband/acc100: update device info Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 27/30] baseband/acc100: add ring companion address Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 28/30] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 29/30] baseband/acc100: configure PMON control registers Hernan Vargas
2022-10-19 0:39 ` [PATCH v4 30/30] baseband/acc100: update guide docs Hernan Vargas
2022-10-20 9:59 ` [EXT] " Akhil Goyal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221019003918.257506-3-hernan.vargas@intel.com \
--to=hernan.vargas@intel.com \
--cc=dev@dpdk.org \
--cc=gakhil@marvell.com \
--cc=maxime.coquelin@redhat.com \
--cc=nicolas.chautru@intel.com \
--cc=qi.z.zhang@intel.com \
--cc=stable@dpdk.org \
--cc=trix@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).