From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A8D4A09F2; Wed, 19 Oct 2022 23:00:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9193042CB4; Wed, 19 Oct 2022 22:58:43 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2042.outbound.protection.outlook.com [40.107.93.42]) by mails.dpdk.org (Postfix) with ESMTP id A839542C74 for ; Wed, 19 Oct 2022 22:58:41 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aUV38y6DT092MHg/Qt/ahdIq4JTwTG1LN+46HkI9sAhtJS7e3rtEFgR8uARR6/XaUl/ZXQkdOv4mEHeLm9xKMSuuAYcqM91YQds/6f9CeQkxA8cdn7UaJG/oB47CJ4NlFm1XkfDZtL/LnEDoeQAlSxNiTpqtJvkRup6F7z5tKQB8rlhovgIfaFb7YiEKVqbOajvNvN9dG3KHOvOVRqsZGVI3bYOxSnUyxjFChE5oKnQdhU5CtSP0pCjBNOBNPclbBMYTUdbaew39STb67w5+kHas3f9QUUajZ6e/iJzuzgKgiYCS4oUtP865tvbf4eh+KTUK1hFYyy9e8elEw71lJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YBalSvz+k8Rxb97TogcGHAO12dF/GXvtygb+BZqeUCI=; b=kQa0IAYwEwdrcna9NVgYxRCVbhVDHl+hxs7K75DA4q65z+ljcV63zqFt35N6z/8oTVrxfCk7U+zHkkoXzwMwhC8NtfAV47VQiDv4NuelI3iwK88GIq3GqJdqO5V8ob3n966fffRXzvpM+Fe3HZhEgJNJMqs2Ej2LZNwp4MZLylIJf5YOn1VQAQL4CSoj+aS4i1vMEL6E9OLM7QzjAlIPRaC6OI3nza2aAez6gMA331TOyB/Cm/FcR88Fo0CvMqMQPx0dA2b68JPwx2l3DgCjMkuDvgcONHm3fC0lnPEzGUS1wa4weiGjtcTi/u0rXBH0YSb5ddBt5xlLm70y1Uwvww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YBalSvz+k8Rxb97TogcGHAO12dF/GXvtygb+BZqeUCI=; b=LYanZ78x2+oxkLDVI+7dkvYyFyUgPHL2OxtxLj2a2DFUH95h0wHTRSKTqYszgSlst1Cw19mHIPBZKP4dD/9JhmmgZ//g20gu8/LE2nF0XIDHI2bOKKHmxQKxyrjmvvo/qvYNragZxbvVKtuoIyrwJ8xJhE1wYeZtSJB6W30ql1TriwIyCyXLLj/NuwkQAnM/q92RpOHPMCMVZKWSKMAcYYcMCBkARc4/3Sf+EbTz0Qly9Eo69YtUMIw4WNxavqm3IzNnvDw8T0YsKJNdl4QDUXYFgibvWNSJelnDddElXF9GsI+v/lPHmc5hojenlldm9D6jTPr/WiYoIB3bi98lRw== Received: from DS7PR03CA0246.namprd03.prod.outlook.com (2603:10b6:5:3b3::11) by SN7PR12MB7451.namprd12.prod.outlook.com (2603:10b6:806:29b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.33; Wed, 19 Oct 2022 20:58:40 +0000 Received: from DM6NAM11FT104.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b3:cafe::af) by DS7PR03CA0246.outlook.office365.com (2603:10b6:5:3b3::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.34 via Frontend Transport; Wed, 19 Oct 2022 20:58:39 +0000 X-MS-Exchange-Authentication-Results: spf=none (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=nvidia.com; Received-SPF: None (protection.outlook.com: nvidia.com does not designate permitted sender hosts) Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT104.mail.protection.outlook.com (10.13.173.232) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.16 via Frontend Transport; Wed, 19 Oct 2022 20:58:39 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 19 Oct 2022 13:58:21 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 19 Oct 2022 13:58:19 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , , Hamdan Igbaria Subject: [v5 17/18] net/mlx5/hws: Add HWS debug layer Date: Wed, 19 Oct 2022 23:57:20 +0300 Message-ID: <20221019205721.8077-18-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221019205721.8077-1-valex@nvidia.com> References: <20220922190345.394-1-valex@nvidia.com> <20221019205721.8077-1-valex@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT104:EE_|SN7PR12MB7451:EE_ X-MS-Office365-Filtering-Correlation-Id: 90bf7ac3-fd03-4d05-2d62-08dab214b2fa X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: J7z25RDIRGRvH/x5C2cpjEKFpk25t3DgHbdjDW6GkuRuPow05IFjPqm8FIgn1YHgSzipjj39qtWUr8arVcNv1LrxLg+7toWu7olnEYH4THCbBYoVzIdzSvyzi4yEAhgbYLtkea17RT4olM8x3VJrGdtcaDko/FoWqbJPliSVi/oAkdiC1RxAa4vguGFavdS9HXQfbKl/OcTvS1Jgn9zZ+487KwkKSluhQ+Jr6FpuRGEptLQhzjX9p33DmlrwA97NfCYRoKY2E1Q9r0Bn1Gy17h6/+NJgagTPMdc+s2QO+TUG+jwoYvyrIVuqg6ymgIeudg6Osdz3TVueP1F1M4Zgep2iFth9XZCcm3x0ipU4SOco616aetBW6koIzCJBJ1axNCBdAFpsSs+VxweKWPAdNyeot7rKiF6CZx0PxCa3f4M88RWCs10Rx045YLoJu0nioqGu3VW7URUQ+dnmaK6BWGywrNMZ1JIBkyRKfky54C8VPOEXQOXi4NFosc3Atxc4aA819KcPwH5A+7w70JkJ5Lujcag0jju+g2r4AH1lGt00jfEV6MqB9pxYzyqa7tizBuOgI3nVqUAdgDXEMMz8DWVFDr2npY05m0u95ofwR7ojisKOvyZvQobdO94XsLs1ndJzyBk1MLakROLFLuQqXbu+Oj+XYH9gJhvwnQ77PJg+l/yR9qGk6SMIsnx6m8l7gD0mhluPwTSuvCv223Un9wgh9gzbY7vCHR+5YsJaIdHK0OHUsUzhv+/xpOO2AqRKbioGOdebj9QnWXB9mjVtMA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(396003)(376002)(39860400002)(136003)(451199015)(46966006)(40470700004)(36840700001)(478600001)(8936002)(107886003)(6666004)(41300700001)(110136005)(54906003)(8676002)(4326008)(36756003)(7696005)(36860700001)(55016003)(40480700001)(70586007)(356005)(40460700003)(82310400005)(2616005)(86362001)(82740400003)(1076003)(7636003)(16526019)(316002)(26005)(336012)(6286002)(83380400001)(186003)(47076005)(426003)(2906002)(6636002)(70206006)(5660300002)(30864003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2022 20:58:39.4895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90bf7ac3-fd03-4d05-2d62-08dab214b2fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT104.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7451 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hamdan Igbaria The debug layer is used to generate a debug CSV file containing details of the context, table, matcher, rules and other useful debug information. Signed-off-by: Hamdan Igbaria Signed-off-by: Alex Vesker --- drivers/net/mlx5/hws/mlx5dr_debug.c | 462 ++++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_debug.h | 28 ++ 2 files changed, 490 insertions(+) create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.c create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.h diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c new file mode 100644 index 0000000000..890a761c48 --- /dev/null +++ b/drivers/net/mlx5/hws/mlx5dr_debug.c @@ -0,0 +1,462 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2022 NVIDIA Corporation & Affiliates + */ + +#include "mlx5dr_internal.h" + +const char *mlx5dr_debug_action_type_str[] = { + [MLX5DR_ACTION_TYP_LAST] = "LAST", + [MLX5DR_ACTION_TYP_TNL_L2_TO_L2] = "TNL_L2_TO_L2", + [MLX5DR_ACTION_TYP_L2_TO_TNL_L2] = "L2_TO_TNL_L2", + [MLX5DR_ACTION_TYP_TNL_L3_TO_L2] = "TNL_L3_TO_L2", + [MLX5DR_ACTION_TYP_L2_TO_TNL_L3] = "L2_TO_TNL_L3", + [MLX5DR_ACTION_TYP_DROP] = "DROP", + [MLX5DR_ACTION_TYP_TIR] = "TIR", + [MLX5DR_ACTION_TYP_FT] = "FT", + [MLX5DR_ACTION_TYP_CTR] = "CTR", + [MLX5DR_ACTION_TYP_TAG] = "TAG", + [MLX5DR_ACTION_TYP_MODIFY_HDR] = "MODIFY_HDR", + [MLX5DR_ACTION_TYP_VPORT] = "VPORT", + [MLX5DR_ACTION_TYP_MISS] = "DEFAULT_MISS", + [MLX5DR_ACTION_TYP_POP_VLAN] = "POP_VLAN", + [MLX5DR_ACTION_TYP_PUSH_VLAN] = "PUSH_VLAN", + [MLX5DR_ACTION_TYP_ASO_METER] = "ASO_METER", + [MLX5DR_ACTION_TYP_ASO_CT] = "ASO_CT", +}; + +static_assert(ARRAY_SIZE(mlx5dr_debug_action_type_str) == MLX5DR_ACTION_TYP_MAX, + "Missing mlx5dr_debug_action_type_str"); + +const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type) +{ + return mlx5dr_debug_action_type_str[action_type]; +} + +static int +mlx5dr_debug_dump_matcher_template_definer(FILE *f, + struct mlx5dr_match_template *mt) +{ + struct mlx5dr_definer *definer = mt->definer; + int i, ret; + + ret = fprintf(f, "%d,0x%" PRIx64 ",0x%" PRIx64 ",%d,%d,", + MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_DEFINER, + (uint64_t)(uintptr_t)definer, + (uint64_t)(uintptr_t)mt, + definer->obj->id, + definer->type); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + for (i = 0; i < DW_SELECTORS; i++) { + ret = fprintf(f, "0x%x%s", definer->dw_selector[i], + (i == DW_SELECTORS - 1) ? "," : "-"); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + } + + for (i = 0; i < BYTE_SELECTORS; i++) { + ret = fprintf(f, "0x%x%s", definer->byte_selector[i], + (i == BYTE_SELECTORS - 1) ? "," : "-"); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + } + + for (i = 0; i < MLX5DR_JUMBO_TAG_SZ; i++) { + ret = fprintf(f, "%02x", definer->mask.jumbo[i]); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + } + + ret = fprintf(f, "\n"); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + return 0; +} + +static int +mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher *matcher) +{ + bool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL; + int i, ret; + + for (i = 0; i < matcher->num_of_mt; i++) { + struct mlx5dr_match_template *mt = matcher->mt[i]; + + ret = fprintf(f, "%d,0x%" PRIx64 ",0x%" PRIx64 ",%d,%d\n", + MLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE, + (uint64_t)(uintptr_t)mt, + (uint64_t)(uintptr_t)matcher, + is_root ? 0 : mt->fc_sz, + mt->flags); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + if (!is_root) { + ret = mlx5dr_debug_dump_matcher_template_definer(f, mt); + if (ret) + return ret; + } + } + + return 0; +} + +static int +mlx5dr_debug_dump_matcher_action_template(FILE *f, struct mlx5dr_matcher *matcher) +{ + bool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL; + enum mlx5dr_action_type action_type; + int i, j, ret; + + for (i = 0; i < matcher->num_of_at; i++) { + struct mlx5dr_action_template *at = matcher->at[i]; + + ret = fprintf(f, "%d,0x%" PRIx64 ",0x%" PRIx64 ",%d,%d,%d", + MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE, + (uint64_t)(uintptr_t)at, + (uint64_t)(uintptr_t)matcher, + at->only_term ? 0 : 1, + is_root ? 0 : at->num_of_action_stes, + at->num_actions); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + for (j = 0; j < at->num_actions; j++) { + action_type = at->action_type_arr[j]; + ret = fprintf(f, ",%s", mlx5dr_debug_action_type_to_str(action_type)); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + } + + fprintf(f, "\n"); + } + + return 0; +} + +static int +mlx5dr_debug_dump_matcher_attr(FILE *f, struct mlx5dr_matcher *matcher) +{ + struct mlx5dr_matcher_attr *attr = &matcher->attr; + int ret; + + ret = fprintf(f, "%d,0x%" PRIx64 ",%d,%d,%d,%d,%d,%d\n", + MLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR, + (uint64_t)(uintptr_t)matcher, + attr->priority, + attr->mode, + attr->table.sz_row_log, + attr->table.sz_col_log, + attr->optimize_using_rule_idx, + attr->optimize_flow_src); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + return 0; +} + +static int mlx5dr_debug_dump_matcher(FILE *f, struct mlx5dr_matcher *matcher) +{ + bool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL; + enum mlx5dr_table_type tbl_type = matcher->tbl->type; + struct mlx5dr_devx_obj *ste_0, *ste_1 = NULL; + struct mlx5dr_pool_chunk *ste; + struct mlx5dr_pool *ste_pool; + int ret; + + ret = fprintf(f, "%d,0x%" PRIx64 ",0x%" PRIx64 ",%d,%d,0x%" PRIx64, + MLX5DR_DEBUG_RES_TYPE_MATCHER, + (uint64_t)(uintptr_t)matcher, + (uint64_t)(uintptr_t)matcher->tbl, + matcher->num_of_mt, + is_root ? 0 : matcher->end_ft->id, + matcher->col_matcher ? (uint64_t)(uintptr_t)matcher->col_matcher : 0); + if (ret < 0) + goto out_err; + + ste = &matcher->match_ste.ste; + ste_pool = matcher->match_ste.pool; + if (ste_pool) { + ste_0 = mlx5dr_pool_chunk_get_base_devx_obj(ste_pool, ste); + if (tbl_type == MLX5DR_TABLE_TYPE_FDB) + ste_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(ste_pool, ste); + } else { + ste_0 = NULL; + ste_1 = NULL; + } + + ret = fprintf(f, ",%d,%d,%d,%d", + matcher->match_ste.rtc_0 ? matcher->match_ste.rtc_0->id : 0, + ste_0 ? (int)ste_0->id : -1, + matcher->match_ste.rtc_1 ? matcher->match_ste.rtc_1->id : 0, + ste_1 ? (int)ste_1->id : -1); + if (ret < 0) + goto out_err; + + ste = &matcher->action_ste.ste; + ste_pool = matcher->action_ste.pool; + if (ste_pool) { + ste_0 = mlx5dr_pool_chunk_get_base_devx_obj(ste_pool, ste); + if (tbl_type == MLX5DR_TABLE_TYPE_FDB) + ste_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(ste_pool, ste); + } else { + ste_0 = NULL; + ste_1 = NULL; + } + + ret = fprintf(f, ",%d,%d,%d,%d\n", + matcher->action_ste.rtc_0 ? matcher->action_ste.rtc_0->id : 0, + ste_0 ? (int)ste_0->id : -1, + matcher->action_ste.rtc_1 ? matcher->action_ste.rtc_1->id : 0, + ste_1 ? (int)ste_1->id : -1); + if (ret < 0) + goto out_err; + + ret = mlx5dr_debug_dump_matcher_attr(f, matcher); + if (ret) + return ret; + + ret = mlx5dr_debug_dump_matcher_match_template(f, matcher); + if (ret) + return ret; + + ret = mlx5dr_debug_dump_matcher_action_template(f, matcher); + if (ret) + return ret; + + return 0; + +out_err: + rte_errno = EINVAL; + return rte_errno; +} + +static int mlx5dr_debug_dump_table(FILE *f, struct mlx5dr_table *tbl) +{ + bool is_root = tbl->level == MLX5DR_ROOT_LEVEL; + struct mlx5dr_matcher *matcher; + int ret; + + ret = fprintf(f, "%d,0x%" PRIx64 ",0x%" PRIx64 ",%d,%d,%d,%d\n", + MLX5DR_DEBUG_RES_TYPE_TABLE, + (uint64_t)(uintptr_t)tbl, + (uint64_t)(uintptr_t)tbl->ctx, + is_root ? 0 : tbl->ft->id, + tbl->type, + is_root ? 0 : tbl->fw_ft_type, + tbl->level); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + LIST_FOREACH(matcher, &tbl->head, next) { + ret = mlx5dr_debug_dump_matcher(f, matcher); + if (ret) + return ret; + } + + return 0; +} + +static int +mlx5dr_debug_dump_context_send_engine(FILE *f, struct mlx5dr_context *ctx) +{ + struct mlx5dr_send_engine *send_queue; + int ret, i, j; + + for (i = 0; i < (int)ctx->queues; i++) { + send_queue = &ctx->send_queue[i]; + ret = fprintf(f, "%d,0x%" PRIx64 ",%d,%d,%d,%d,%d,%d,%d,%d,%d\n", + MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE, + (uint64_t)(uintptr_t)ctx, + i, + send_queue->used_entries, + send_queue->th_entries, + send_queue->rings, + send_queue->num_entries, + send_queue->err, + send_queue->completed.ci, + send_queue->completed.pi, + send_queue->completed.mask); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + for (j = 0; j < MLX5DR_NUM_SEND_RINGS; j++) { + struct mlx5dr_send_ring *send_ring = &send_queue->send_ring[j]; + struct mlx5dr_send_ring_cq *cq = &send_ring->send_cq; + struct mlx5dr_send_ring_sq *sq = &send_ring->send_sq; + + ret = fprintf(f, "%d,0x%" PRIx64 ",%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", + MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING, + (uint64_t)(uintptr_t)ctx, + j, + i, + cq->cqn, + cq->cons_index, + cq->ncqe_mask, + cq->buf_sz, + cq->ncqe, + cq->cqe_log_sz, + cq->poll_wqe, + cq->cqe_sz, + sq->sqn, + sq->obj->id, + sq->cur_post, + sq->buf_mask); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + } + } + + return 0; +} + +static int mlx5dr_debug_dump_context_caps(FILE *f, struct mlx5dr_context *ctx) +{ + struct mlx5dr_cmd_query_caps *caps = ctx->caps; + int ret; + + ret = fprintf(f, "%d,0x%" PRIx64 ",%s,%d,%d,%d,%d,", + MLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS, + (uint64_t)(uintptr_t)ctx, + caps->fw_ver, + caps->wqe_based_update, + caps->ste_format, + caps->ste_alloc_log_max, + caps->log_header_modify_argument_max_alloc); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + ret = fprintf(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", + caps->flex_protocols, + caps->rtc_reparse_mode, + caps->rtc_index_mode, + caps->ste_alloc_log_gran, + caps->stc_alloc_log_max, + caps->stc_alloc_log_gran, + caps->rtc_log_depth_max, + caps->format_select_gtpu_dw_0, + caps->format_select_gtpu_dw_1, + caps->format_select_gtpu_dw_2, + caps->format_select_gtpu_ext_dw_0, + caps->nic_ft.max_level, + caps->nic_ft.reparse, + caps->fdb_ft.max_level, + caps->fdb_ft.reparse, + caps->log_header_modify_argument_granularity); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + return 0; +} + +static int mlx5dr_debug_dump_context_attr(FILE *f, struct mlx5dr_context *ctx) +{ + int ret; + + ret = fprintf(f, "%u,0x%" PRIx64 ",%d,%zu,%d\n", + MLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR, + (uint64_t)(uintptr_t)ctx, + ctx->pd_num, + ctx->queues, + ctx->send_queue->num_entries); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + return 0; +} + +static int mlx5dr_debug_dump_context_info(FILE *f, struct mlx5dr_context *ctx) +{ + int ret; + + ret = fprintf(f, "%d,0x%" PRIx64 ",%d,%s,%s\n", + MLX5DR_DEBUG_RES_TYPE_CONTEXT, + (uint64_t)(uintptr_t)ctx, + ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT, + mlx5_glue->get_device_name(ctx->ibv_ctx->device), + DEBUG_VERSION); + if (ret < 0) { + rte_errno = EINVAL; + return rte_errno; + } + + ret = mlx5dr_debug_dump_context_attr(f, ctx); + if (ret) + return ret; + + ret = mlx5dr_debug_dump_context_caps(f, ctx); + if (ret) + return ret; + + return 0; +} + +static int mlx5dr_debug_dump_context(FILE *f, struct mlx5dr_context *ctx) +{ + struct mlx5dr_table *tbl; + int ret; + + ret = mlx5dr_debug_dump_context_info(f, ctx); + if (ret) + return ret; + + ret = mlx5dr_debug_dump_context_send_engine(f, ctx); + if (ret) + return ret; + + LIST_FOREACH(tbl, &ctx->head, next) { + ret = mlx5dr_debug_dump_table(f, tbl); + if (ret) + return ret; + } + + return 0; +} + +int mlx5dr_debug_dump(struct mlx5dr_context *ctx, FILE *f) +{ + int ret; + + if (!f || !ctx) { + rte_errno = EINVAL; + return -rte_errno; + } + + pthread_spin_lock(&ctx->ctrl_lock); + ret = mlx5dr_debug_dump_context(f, ctx); + pthread_spin_unlock(&ctx->ctrl_lock); + + return -ret; +} diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.h b/drivers/net/mlx5/hws/mlx5dr_debug.h new file mode 100644 index 0000000000..cf00170f7d --- /dev/null +++ b/drivers/net/mlx5/hws/mlx5dr_debug.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2022 NVIDIA Corporation & Affiliates + */ + +#ifndef MLX5DR_DEBUG_H_ +#define MLX5DR_DEBUG_H_ + +#define DEBUG_VERSION "1.0.DPDK" + +enum mlx5dr_debug_res_type { + MLX5DR_DEBUG_RES_TYPE_CONTEXT = 4000, + MLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR = 4001, + MLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS = 4002, + MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE = 4003, + MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING = 4004, + + MLX5DR_DEBUG_RES_TYPE_TABLE = 4100, + + MLX5DR_DEBUG_RES_TYPE_MATCHER = 4200, + MLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR = 4201, + MLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE = 4202, + MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204, + MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_DEFINER = 4203, +}; + +const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type); + +#endif /* MLX5DR_DEBUG_H_ */ -- 2.18.1