From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 90820A0552; Thu, 20 Oct 2022 23:27:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3408742C45; Thu, 20 Oct 2022 23:25:14 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id AF16E42C2C for ; Thu, 20 Oct 2022 23:25:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301108; x=1697837108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tPBOkEwKOXMhl3og3EQSQuZyO6z/sJsxMw/bY++NRfI=; b=UGONVDs+r0rtX3J86N/vgXcGkTGbk42dRSxxGHCPYQ0R8lroC9yZ+1kz 89POl/wPiy0MrebqSgNF8FcHGq2gReaJ4WzclLHlwfXOmDe5RwGtuMBm8 bKQV5hRimKFhMs1ymM+5PvsmT5bPCqw1ihij4qoB+tWa8sWhreeV4RPXx E676hjMkaFgPnuvKOv496fQZe1KjBO6Uk8ZFKx/vvoM/Eg3xCxbH3py/g VZMGkB7wBSX+nval+VEFglOqNXdKnXqvXNIet110rXIKOSIpwLMQvcRa7 /qPvpIeCuNbImbFML/88VCQb0Uh5bjJPuzzkgaZnTrIUHf0xq/SY6aLQd g==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887532" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887532" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396967" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396967" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:44 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 29/29] baseband/acc100: configure PMON control registers Date: Thu, 20 Oct 2022 22:21:02 -0700 Message-Id: <20221021052102.107141-30-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable performance monitor control registers. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc100_pmd.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index eb6349c85a..8c0aec5ed8 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -115,6 +115,8 @@ struct acc100_registry_addr { unsigned int depth_log1_offset; unsigned int qman_group_func; unsigned int ddr_range; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; }; /* Structure holding registry addresses for PF */ @@ -144,6 +146,8 @@ static const struct acc100_registry_addr pf_reg_addr = { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; /* Structure holding registry addresses for VF */ -- 2.37.1