From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D094DA054A; Tue, 25 Oct 2022 11:09:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51C5D42C00; Tue, 25 Oct 2022 11:09:25 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 2699942BB8 for ; Tue, 25 Oct 2022 11:09:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666688960; x=1698224960; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2NdhufRzKZ4FuidA09J4/gJ+qkGcqQ35Ptx0x5WW+50=; b=T0GkZhr0JXJHV8AoiRpR3IK0SGvaw6Tc9wqN20YoIC1hXp1mHIy98+02 cn+2q7xQuJqLHFGXofAlHNxl1I7sFIgLcS6xSdNdnGtxXT0W7GL8368/Q 6LSHP2940bfhb3PM9nC8gVn6YYkyuubeO+REKbDcZY4fHi3vRA/bnt9gL 1KgWC8RmvAL2VRTG2wSvX4q+gtGHljZEAaNcqENS/R43uPjLxHlAR07jJ o4+UKk8HuLVffDYRPWQ3WgMZ4YMP4IKZH4AVIOTiUDI5GbAfzpfZavZTG m/1DPBDTlZDx1B4RwMpqdgDAeJplZutcIAd6uE7J1ih9xhSTK9muYLLki g==; X-IronPort-AV: E=McAfee;i="6500,9779,10510"; a="306358811" X-IronPort-AV: E=Sophos;i="5.95,211,1661842800"; d="scan'208";a="306358811" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2022 02:09:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10510"; a="756864548" X-IronPort-AV: E=Sophos;i="5.95,211,1661842800"; d="scan'208";a="756864548" Received: from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2022 02:09:16 -0700 From: Junfeng Guo To: qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@xilinx.com, beilei.xing@intel.com Cc: dev@dpdk.org, xiaoyun.li@intel.com, awogbemila@google.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, stephen@networkplumber.org, chenbo.xia@intel.com, helin.zhang@intel.com, Junfeng Guo , Haiyue Wang Subject: [PATCH v8 2/8] net/gve/base: add OS specific implementation Date: Tue, 25 Oct 2022 17:07:23 +0800 Message-Id: <20221025090729.2593603-3-junfeng.guo@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221025090729.2593603-1-junfeng.guo@intel.com> References: <20221021091928.2674471-2-junfeng.guo@intel.com> <20221025090729.2593603-1-junfeng.guo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add some MACRO definitions and memory operations which are specific for DPDK. Signed-off-by: Haiyue Wang Signed-off-by: Xiaoyun Li Signed-off-by: Junfeng Guo --- drivers/net/gve/base/gve_adminq.h | 2 + drivers/net/gve/base/gve_desc.h | 2 + drivers/net/gve/base/gve_desc_dqo.h | 2 + drivers/net/gve/base/gve_osdep.h | 159 ++++++++++++++++++++++++++++ drivers/net/gve/base/gve_register.h | 2 + 5 files changed, 167 insertions(+) create mode 100644 drivers/net/gve/base/gve_osdep.h diff --git a/drivers/net/gve/base/gve_adminq.h b/drivers/net/gve/base/gve_adminq.h index b2422d7dc8..05550119de 100644 --- a/drivers/net/gve/base/gve_adminq.h +++ b/drivers/net/gve/base/gve_adminq.h @@ -6,6 +6,8 @@ #ifndef _GVE_ADMINQ_H #define _GVE_ADMINQ_H +#include "gve_osdep.h" + /* Admin queue opcodes */ enum gve_adminq_opcodes { GVE_ADMINQ_DESCRIBE_DEVICE = 0x1, diff --git a/drivers/net/gve/base/gve_desc.h b/drivers/net/gve/base/gve_desc.h index e0bbadcfd4..006b36442f 100644 --- a/drivers/net/gve/base/gve_desc.h +++ b/drivers/net/gve/base/gve_desc.h @@ -8,6 +8,8 @@ #ifndef _GVE_DESC_H_ #define _GVE_DESC_H_ +#include "gve_osdep.h" + /* A note on seg_addrs * * Base addresses encoded in seg_addr are not assumed to be physical diff --git a/drivers/net/gve/base/gve_desc_dqo.h b/drivers/net/gve/base/gve_desc_dqo.h index 9965f190d1..ee1afdecb8 100644 --- a/drivers/net/gve/base/gve_desc_dqo.h +++ b/drivers/net/gve/base/gve_desc_dqo.h @@ -8,6 +8,8 @@ #ifndef _GVE_DESC_DQO_H_ #define _GVE_DESC_DQO_H_ +#include "gve_osdep.h" + #define GVE_TX_MAX_HDR_SIZE_DQO 255 #define GVE_TX_MIN_TSO_MSS_DQO 88 diff --git a/drivers/net/gve/base/gve_osdep.h b/drivers/net/gve/base/gve_osdep.h new file mode 100644 index 0000000000..7cb73002f4 --- /dev/null +++ b/drivers/net/gve/base/gve_osdep.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Intel Corporation + */ + +#ifndef _GVE_OSDEP_H_ +#define _GVE_OSDEP_H_ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../gve_logs.h" + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +typedef rte_be16_t __sum16; + +typedef rte_be16_t __be16; +typedef rte_be32_t __be32; +typedef rte_be64_t __be64; + +typedef rte_iova_t dma_addr_t; + +#define ETH_MIN_MTU RTE_ETHER_MIN_MTU +#define ETH_ALEN RTE_ETHER_ADDR_LEN + +#ifndef PAGE_SHIFT +#define PAGE_SHIFT 12 +#endif +#ifndef PAGE_SIZE +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#endif + +#define BIT(nr) RTE_BIT32(nr) + +#define be16_to_cpu(x) rte_be_to_cpu_16(x) +#define be32_to_cpu(x) rte_be_to_cpu_32(x) +#define be64_to_cpu(x) rte_be_to_cpu_64(x) + +#define cpu_to_be16(x) rte_cpu_to_be_16(x) +#define cpu_to_be32(x) rte_cpu_to_be_32(x) +#define cpu_to_be64(x) rte_cpu_to_be_64(x) + +#define READ_ONCE32(x) rte_read32(&(x)) + +#ifndef ____cacheline_aligned +#define ____cacheline_aligned __rte_cache_aligned +#endif +#ifndef __packed +#define __packed __rte_packed +#endif +#define __iomem + +#define msleep(ms) rte_delay_ms(ms) + +/* These macros are used to generate compilation errors if a struct/union + * is not exactly the correct length. It gives a divide by zero error if + * the struct/union is not of the correct size, otherwise it creates an + * enum that is never used. + */ +#define GVE_CHECK_STRUCT_LEN(n, X) enum gve_static_assert_enum_##X \ + { gve_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) } +#define GVE_CHECK_UNION_LEN(n, X) enum gve_static_asset_enum_##X \ + { gve_static_assert_##X = (n) / ((sizeof(union X) == (n)) ? 1 : 0) } + +static __rte_always_inline u8 +readb(volatile void *addr) +{ + return rte_read8(addr); +} + +static __rte_always_inline void +writeb(u8 value, volatile void *addr) +{ + rte_write8(value, addr); +} + +static __rte_always_inline void +writel(u32 value, volatile void *addr) +{ + rte_write32(value, addr); +} + +static __rte_always_inline u32 +ioread32be(const volatile void *addr) +{ + return rte_be_to_cpu_32(rte_read32(addr)); +} + +static __rte_always_inline void +iowrite32be(u32 value, volatile void *addr) +{ + writel(rte_cpu_to_be_32(value), addr); +} + +/* DMA memory allocation tracking */ +struct gve_dma_mem { + void *va; + rte_iova_t pa; + uint32_t size; + const void *zone; +}; + +static inline void * +gve_alloc_dma_mem(struct gve_dma_mem *mem, u64 size) +{ + static uint16_t gve_dma_memzone_id; + const struct rte_memzone *mz = NULL; + char z_name[RTE_MEMZONE_NAMESIZE]; + + if (!mem) + return NULL; + + snprintf(z_name, sizeof(z_name), "gve_dma_%u", + __atomic_fetch_add(&gve_dma_memzone_id, 1, __ATOMIC_RELAXED)); + mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, + RTE_MEMZONE_IOVA_CONTIG, + PAGE_SIZE); + if (!mz) + return NULL; + + mem->size = size; + mem->va = mz->addr; + mem->pa = mz->iova; + mem->zone = mz; + PMD_DRV_LOG(DEBUG, "memzone %s is allocated", mz->name); + + return mem->va; +} + +static inline void +gve_free_dma_mem(struct gve_dma_mem *mem) +{ + PMD_DRV_LOG(DEBUG, "memzone %s to be freed", + ((const struct rte_memzone *)mem->zone)->name); + + rte_memzone_free(mem->zone); + mem->zone = NULL; + mem->va = NULL; + mem->pa = 0; +} + +#endif /* _GVE_OSDEP_H_ */ diff --git a/drivers/net/gve/base/gve_register.h b/drivers/net/gve/base/gve_register.h index bf7f102cde..c674167f31 100644 --- a/drivers/net/gve/base/gve_register.h +++ b/drivers/net/gve/base/gve_register.h @@ -6,6 +6,8 @@ #ifndef _GVE_REGISTER_H_ #define _GVE_REGISTER_H_ +#include "gve_osdep.h" + /* Fixed Configuration Registers */ struct gve_registers { __be32 device_status; -- 2.34.1