From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B339FA0542; Fri, 11 Nov 2022 10:44:04 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7BED642D26; Fri, 11 Nov 2022 10:43:57 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1B11942D2B for ; Fri, 11 Nov 2022 10:43:56 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AB91EGh006339; Fri, 11 Nov 2022 01:43:53 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QZTt1anb85jQNVehsRXv5S4SdJg15gsPiJh//UTiCYg=; b=PlgQ4kW/ccXrllw9SLPq9a9Im7wgPt9s/AUs2JjgO/lveTUQefYx5aRPudfdcgQPhN4Y gbIj3dFjbYV5o6rT7KGi39yr8B9QEpuzfAJ6pgtuN9ZR7luEmtcUYQRTDc8tIDJuKik/ PC6Z0ABVRkSPENl0LwwZL+Rlx4y16iD0h1yomTyfc+3QyNUtNPICqeitEDKdgOThxaXJ 0sCc2eee8SPci8sdS0gW4jUi9G1xxprRh3+El7an6/AbmzB6oveE26D9mQG1yDKaOBr7 1N2Mr0xleCPepllaHhBberDSWPOPNPv6EZuBtWkHt4jB0nML6BGnFBieh4N1Nugwyw9q MQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kskck03w4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 11 Nov 2022 01:43:53 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 11 Nov 2022 01:43:50 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Nov 2022 01:43:50 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 167CF5B6926; Fri, 11 Nov 2022 01:43:48 -0800 (PST) From: Tomasz Duszynski To: , , Ruifeng Wang CC: , Subject: [PATCH 2/4] eal/arm: support reading ARM PMU events in runtime Date: Fri, 11 Nov 2022 10:43:36 +0100 Message-ID: <20221111094338.2736065-3-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111094338.2736065-1-tduszynski@marvell.com> References: <20221111094338.2736065-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 0MiesDvWEWgiZ9nmctb7rl1SNIllWMbD X-Proofpoint-ORIG-GUID: 0MiesDvWEWgiZ9nmctb7rl1SNIllWMbD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-11_05,2022-11-09_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for reading ARM PMU events in runtime. Signed-off-by: Tomasz Duszynski --- app/test/test_pmu.c | 4 ++ lib/eal/arm/include/meson.build | 1 + lib/eal/arm/include/rte_pmu_pmc.h | 37 +++++++++++ lib/eal/arm/meson.build | 4 ++ lib/eal/arm/rte_pmu.c | 103 ++++++++++++++++++++++++++++++ lib/eal/include/rte_pmu.h | 3 + 6 files changed, 152 insertions(+) create mode 100644 lib/eal/arm/include/rte_pmu_pmc.h create mode 100644 lib/eal/arm/rte_pmu.c diff --git a/app/test/test_pmu.c b/app/test/test_pmu.c index fd331af9ee..f94866dff9 100644 --- a/app/test/test_pmu.c +++ b/app/test/test_pmu.c @@ -13,6 +13,10 @@ test_pmu_read(void) int tries = 10; int event = -1; +#if defined(RTE_ARCH_ARM64) + event = rte_pmu_add_event("cpu_cycles"); +#endif + while (tries--) val += rte_pmu_read(event); diff --git a/lib/eal/arm/include/meson.build b/lib/eal/arm/include/meson.build index 657bf58569..ab13b0220a 100644 --- a/lib/eal/arm/include/meson.build +++ b/lib/eal/arm/include/meson.build @@ -20,6 +20,7 @@ arch_headers = files( 'rte_pause_32.h', 'rte_pause_64.h', 'rte_pause.h', + 'rte_pmu_pmc.h', 'rte_power_intrinsics.h', 'rte_prefetch_32.h', 'rte_prefetch_64.h', diff --git a/lib/eal/arm/include/rte_pmu_pmc.h b/lib/eal/arm/include/rte_pmu_pmc.h new file mode 100644 index 0000000000..5efc851cb8 --- /dev/null +++ b/lib/eal/arm/include/rte_pmu_pmc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Marvell. + */ + +#ifndef _RTE_PMU_PMC_ARM_H_ +#define _RTE_PMU_PMC_ARM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +static __rte_always_inline uint64_t +rte_pmu_pmc_read(int index) +{ + uint64_t val; + + if (index == 31) { + /* CPU Cycles (0x11) must be read via pmccntr_el0 */ + asm volatile("mrs %0, pmccntr_el0" : "=r" (val)); + } else { + asm volatile( + "msr pmselr_el0, %x0\n" + "mrs %0, pmxevcntr_el0\n" + : "=r" (val) + : "rZ" (index) + ); + } + + return val; +} +#define rte_pmu_pmc_read rte_pmu_pmc_read + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PMU_PMC_ARM_H_ */ diff --git a/lib/eal/arm/meson.build b/lib/eal/arm/meson.build index dca1106aae..0c5575b197 100644 --- a/lib/eal/arm/meson.build +++ b/lib/eal/arm/meson.build @@ -9,3 +9,7 @@ sources += files( 'rte_hypervisor.c', 'rte_power_intrinsics.c', ) + +if is_linux + sources += files('rte_pmu.c') +endif diff --git a/lib/eal/arm/rte_pmu.c b/lib/eal/arm/rte_pmu.c new file mode 100644 index 0000000000..6c50a1b3c4 --- /dev/null +++ b/lib/eal/arm/rte_pmu.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell International Ltd. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include "pmu_private.h" + +#define PERF_USER_ACCESS_PATH "/proc/sys/kernel/perf_user_access" + +static int restore_uaccess; + +static int +read_attr_int(const char *path, int *val) +{ + char buf[BUFSIZ]; + int ret, fd; + + fd = open(path, O_RDONLY); + if (fd == -1) + return -errno; + + ret = read(fd, buf, sizeof(buf)); + if (ret == -1) { + close(fd); + + return -errno; + } + + *val = strtol(buf, NULL, 10); + close(fd); + + return 0; +} + +static int +write_attr_int(const char *path, int val) +{ + char buf[BUFSIZ]; + int num, ret, fd; + + fd = open(path, O_WRONLY); + if (fd == -1) + return -errno; + + num = snprintf(buf, sizeof(buf), "%d", val); + ret = write(fd, buf, num); + if (ret == -1) { + close(fd); + + return -errno; + } + + close(fd); + + return 0; +} + +int +pmu_arch_init(void) +{ + int ret; + + ret = read_attr_int(PERF_USER_ACCESS_PATH, &restore_uaccess); + if (ret) { + RTE_LOG(ERR, EAL, "failed to read %s\n", PERF_USER_ACCESS_PATH); + + return ret; + } + + ret = write_attr_int(PERF_USER_ACCESS_PATH, 1); + if (ret) { + RTE_LOG(ERR, EAL, "failed to enable perf user access\n" + "try enabling manually 'echo 1 > %s'\n", + PERF_USER_ACCESS_PATH); + + return ret; + } + + return 0; +} + +void +pmu_arch_fini(void) +{ + write_attr_int(PERF_USER_ACCESS_PATH, restore_uaccess); +} + +void +pmu_arch_fixup_config(uint64_t config[3]) +{ + /* select 64 bit counters */ + config[1] |= RTE_BIT64(0); + /* enable userspace access */ + config[1] |= RTE_BIT64(1); +} diff --git a/lib/eal/include/rte_pmu.h b/lib/eal/include/rte_pmu.h index 5955c22779..67b1194a2a 100644 --- a/lib/eal/include/rte_pmu.h +++ b/lib/eal/include/rte_pmu.h @@ -20,6 +20,9 @@ extern "C" { #include #include #include +#if defined(RTE_ARCH_ARM64) +#include +#endif /** * @file -- 2.25.1