From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 985C2A055D; Mon, 21 Nov 2022 13:12:08 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 25CD142D27; Mon, 21 Nov 2022 13:11:52 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C7B1842D14 for ; Mon, 21 Nov 2022 13:11:49 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2ALBUWqo014550; Mon, 21 Nov 2022 04:11:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=DDhySMqtcpYJr8Ks//5jW1duVa2Syis5Jz/SwLyP2cw=; b=GRUJ3HR+b4zNTYovssOoGkXzCNrb2iAwtMTDojPfY4fVVwJK5wM7gOWYdVLjkZQ2O/RF OgLoxq7nbeojvp4wohenwhTWf1FNglUmpaxwFpiQI1LEToihIMGMp9YliuUSqI+eJSN4 EXRH/O85AVchY4bPPWbWoryaX02asCravyke0BAonKsYCxWHBjfBJHNPwkPHjKesn9qy rk5H5Tvt8mlZ3KIdvaGMev4kEHO/MOENvh+14HciVqeJ++wwvzADhEPp2/85fguBPWHi 0zVc4pA9+x+9PDa5/KlMrYiLr+vqeYC+r7S2H/FQDMCQ22csl8uhqASDx2A9JZkkY9gb 9w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kxyhrwj36-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 21 Nov 2022 04:11:49 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 21 Nov 2022 04:11:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 21 Nov 2022 04:11:47 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 920143F7072; Mon, 21 Nov 2022 04:11:45 -0800 (PST) From: Tomasz Duszynski To: , Bruce Richardson , "Konstantin Ananyev" CC: , , Tomasz Duszynski Subject: [PATCH v2 3/4] eal/x86: support reading Intel PMU events in runtime Date: Mon, 21 Nov 2022 13:11:20 +0100 Message-ID: <20221121121121.3917194-4-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121121121.3917194-1-tduszynski@marvell.com> References: <20221111094338.2736065-1-tduszynski@marvell.com> <20221121121121.3917194-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: UlvXv-B0sXZhvmyfnFYyAg1nPi-fYUEu X-Proofpoint-ORIG-GUID: UlvXv-B0sXZhvmyfnFYyAg1nPi-fYUEu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-21_13,2022-11-18_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for reading Intel PMU events in runtime. Signed-off-by: Tomasz Duszynski --- app/test/test_pmu.c | 2 ++ lib/eal/include/rte_pmu.h | 2 +- lib/eal/x86/include/meson.build | 1 + lib/eal/x86/include/rte_pmu_pmc.h | 33 +++++++++++++++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 lib/eal/x86/include/rte_pmu_pmc.h diff --git a/app/test/test_pmu.c b/app/test/test_pmu.c index f94866dff9..016204c083 100644 --- a/app/test/test_pmu.c +++ b/app/test/test_pmu.c @@ -15,6 +15,8 @@ test_pmu_read(void) #if defined(RTE_ARCH_ARM64) event = rte_pmu_add_event("cpu_cycles"); +#elif defined(RTE_ARCH_X86_64) + event = rte_pmu_add_event("cpu-cycles"); #endif while (tries--) diff --git a/lib/eal/include/rte_pmu.h b/lib/eal/include/rte_pmu.h index 67b1194a2a..bbe12d100d 100644 --- a/lib/eal/include/rte_pmu.h +++ b/lib/eal/include/rte_pmu.h @@ -20,7 +20,7 @@ extern "C" { #include #include #include -#if defined(RTE_ARCH_ARM64) +#if defined(RTE_ARCH_ARM64) || defined(RTE_ARCH_X86_64) #include #endif diff --git a/lib/eal/x86/include/meson.build b/lib/eal/x86/include/meson.build index 52d2f8e969..03d286ed25 100644 --- a/lib/eal/x86/include/meson.build +++ b/lib/eal/x86/include/meson.build @@ -9,6 +9,7 @@ arch_headers = files( 'rte_io.h', 'rte_memcpy.h', 'rte_pause.h', + 'rte_pmu_pmc.h', 'rte_power_intrinsics.h', 'rte_prefetch.h', 'rte_rtm.h', diff --git a/lib/eal/x86/include/rte_pmu_pmc.h b/lib/eal/x86/include/rte_pmu_pmc.h new file mode 100644 index 0000000000..a2cd849fb1 --- /dev/null +++ b/lib/eal/x86/include/rte_pmu_pmc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Marvell. + */ + +#ifndef _RTE_PMU_PMC_X86_H_ +#define _RTE_PMU_PMC_X86_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +static __rte_always_inline uint64_t +rte_pmu_pmc_read(int index) +{ + uint32_t high, low; + + asm volatile( + "rdpmc\n" + : "=a" (low), "=d" (high) + : "c" (index) + ); + + return ((uint64_t)high << 32) | (uint64_t)low; +} +#define rte_pmu_pmc_read rte_pmu_pmc_read + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PMU_PMC_X86_H_ */ -- 2.25.1