From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 92C74A0093; Thu, 8 Dec 2022 21:03:46 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C9C0842D68; Thu, 8 Dec 2022 21:02:39 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 15BA342BAC for ; Thu, 8 Dec 2022 21:02:29 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B8JjnOA005114 for ; Thu, 8 Dec 2022 12:02:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=jBMnf4FOJVIZAPs0U/dAsrshfPoULr+MtcySaVScGzk=; b=cROVyVRrJhrRYG9FXSxTa/Ydghd3tSjf3BJQEleWzjkkaemg6W3H0iinOCCPqdkY1oOJ WPrAS2xBcUmCv8I3WUKG2denQsdeFADAO2hD4PB0YmLuNg+qSn5W3iml+Uk/Qt5GUv6v ntAjViNkOqzhawgfHI43m5VSn84gN6m0PSIoS6Yp8v8mnFDcGarRRk9ChC3H3Tr4TnLd FLPvXqh8ZF4e9fAsYcE6muVSoDmje2W2CcijteoSZ4bjD7TVYwUrKUHrs/xfh7Psb3wg Tl3z5SOnVOUGxdAX6sLGU8QEz495vORzPRRI7cdR5lR1SLXBNpReLtCAL4LJF/KRDDb6 yw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3m86usnfsn-7 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 08 Dec 2022 12:02:29 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Dec 2022 12:02:25 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Dec 2022 12:02:25 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 6799F3F706C; Thu, 8 Dec 2022 12:02:25 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v1 08/37] ml/cnxk: enable support for device start and stop Date: Thu, 8 Dec 2022 12:01:51 -0800 Message-ID: <20221208200220.20267-9-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221208200220.20267-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: gvxvr4PwA8cVcwWiCy57jHRol__muKOw X-Proofpoint-ORIG-GUID: gvxvr4PwA8cVcwWiCy57jHRol__muKOw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-08_11,2022-12-08_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implemented ML driver functions to start and stop ML device. Start / Stop would enable or disable ML device to accept inference requests. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 42 +++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 11e1cdb7cd..3fea763caf 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -104,9 +104,45 @@ cn10k_ml_dev_close(struct rte_ml_dev *dev) return rte_dev_remove(dev->device); } +static int +cn10k_ml_dev_start(struct rte_ml_dev *dev) +{ + struct cn10k_ml_dev *mldev; + uint64_t reg_val64; + + mldev = dev->data->dev_private; + + reg_val64 = roc_ml_reg_read64(&mldev->roc, ML_CFG); + reg_val64 |= ROC_ML_CFG_ENA; + roc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG); + plt_ml_dbg("ML_CFG => 0x%016lx", roc_ml_reg_read64(&mldev->roc, ML_CFG)); + + mldev->state = ML_CN10K_DEV_STATE_STARTED; + + return 0; +} + +static int +cn10k_ml_dev_stop(struct rte_ml_dev *dev) +{ + struct cn10k_ml_dev *mldev; + uint64_t reg_val64; + + mldev = dev->data->dev_private; + + reg_val64 = roc_ml_reg_read64(&mldev->roc, ML_CFG); + reg_val64 &= ~ROC_ML_CFG_ENA; + roc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG); + plt_ml_dbg("ML_CFG => 0x%016lx", roc_ml_reg_read64(&mldev->roc, ML_CFG)); + + mldev->state = ML_CN10K_DEV_STATE_CONFIGURED; + + return 0; +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ - .dev_info_get = cn10k_ml_dev_info_get, - .dev_configure = cn10k_ml_dev_configure, - .dev_close = cn10k_ml_dev_close, + .dev_info_get = cn10k_ml_dev_info_get, .dev_configure = cn10k_ml_dev_configure, + .dev_close = cn10k_ml_dev_close, .dev_start = cn10k_ml_dev_start, + .dev_stop = cn10k_ml_dev_stop, }; -- 2.17.1