From: Qi Zhang <qi.z.zhang@intel.com>
To: mb@smartsharesystems.com, bruce.richardson@intel.com,
wenzhuo.lu@intel.com
Cc: dev@dpdk.org, wenjun1.wu@intel.com,
Qi Zhang <qi.z.zhang@intel.com>,
stable@dpdk.org
Subject: [PATCH 1/3] net/ice: support no IOVA as PA mode
Date: Sun, 11 Dec 2022 16:52:54 -0500 [thread overview]
Message-ID: <20221211215256.370099-2-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20221211215256.370099-1-qi.z.zhang@intel.com>
Remove buf_iova access when RTE_IOVA_AS_PA is not defined.
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/ice_rxtx_common_avx.h | 24 ++++++++++++++++++++++++
drivers/net/ice/ice_rxtx_vec_avx2.c | 11 +++++------
drivers/net/ice/ice_rxtx_vec_avx512.c | 17 +++++++++++------
3 files changed, 40 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/ice_rxtx_common_avx.h b/drivers/net/ice/ice_rxtx_common_avx.h
index 81e0db5dd3..377740d43b 100644
--- a/drivers/net/ice/ice_rxtx_common_avx.h
+++ b/drivers/net/ice/ice_rxtx_common_avx.h
@@ -11,6 +11,12 @@
#pragma GCC diagnostic ignored "-Wcast-qual"
#endif
+#if RTE_IOVA_AS_PA
+#define _PKT_DATA_OFF_U64(pkt) ((pkt)->buf_iova + (pkt)->data_off)
+#else
+#define _PKT_DATA_OFF_U64(pkt) ((u64)(pkt)->buf_addr + (pkt)->data_off)
+#endif
+
#ifdef __AVX2__
static __rte_always_inline void
ice_rxq_rearm_common(struct ice_rx_queue *rxq, __rte_unused bool avx512)
@@ -54,9 +60,15 @@ ice_rxq_rearm_common(struct ice_rx_queue *rxq, __rte_unused bool avx512)
mb0 = rxep[0].mbuf;
mb1 = rxep[1].mbuf;
+#if RTE_IOVA_AS_PA
/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
offsetof(struct rte_mbuf, buf_addr) + 8);
+#else
+ /* load buf_addr(lo 64bit) and next(hi 64bit) */
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, next) !=
+ offsetof(struct rte_mbuf, buf_addr) + 8);
+#endif
vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
@@ -97,9 +109,15 @@ ice_rxq_rearm_common(struct ice_rx_queue *rxq, __rte_unused bool avx512)
mb6 = rxep[6].mbuf;
mb7 = rxep[7].mbuf;
+#if RTE_IOVA_AS_PA
/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
offsetof(struct rte_mbuf, buf_addr) + 8);
+#else
+ /* load buf_addr(lo 64bit) and next(hi 64bit) */
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, next) !=
+ offsetof(struct rte_mbuf, buf_addr) + 8);
+#endif
vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
@@ -161,9 +179,15 @@ ice_rxq_rearm_common(struct ice_rx_queue *rxq, __rte_unused bool avx512)
mb2 = rxep[2].mbuf;
mb3 = rxep[3].mbuf;
+#if RTE_IOVA_AS_PA
/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
offsetof(struct rte_mbuf, buf_addr) + 8);
+#else
+ /* load buf_addr(lo 64bit) and next(hi 64bit) */
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, next) !=
+ offsetof(struct rte_mbuf, buf_addr) + 8);
+#endif
vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
diff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c b/drivers/net/ice/ice_rxtx_vec_avx2.c
index 31d6af42fd..b0fd51d37e 100644
--- a/drivers/net/ice/ice_rxtx_vec_avx2.c
+++ b/drivers/net/ice/ice_rxtx_vec_avx2.c
@@ -821,8 +821,7 @@ ice_vtx1(volatile struct ice_tx_desc *txdp,
if (offload)
ice_txd_enable_offload(pkt, &high_qw);
- __m128i descriptor = _mm_set_epi64x(high_qw,
- pkt->buf_iova + pkt->data_off);
+ __m128i descriptor = _mm_set_epi64x(high_qw, _PKT_DATA_OFF_U64(pkt));
_mm_store_si128((__m128i *)txdp, descriptor);
}
@@ -869,15 +868,15 @@ ice_vtx(volatile struct ice_tx_desc *txdp,
__m256i desc2_3 =
_mm256_set_epi64x
(hi_qw3,
- pkt[3]->buf_iova + pkt[3]->data_off,
+ _PKT_DATA_OFF_U64(pkt[3]),
hi_qw2,
- pkt[2]->buf_iova + pkt[2]->data_off);
+ _PKT_DATA_OFF_U64(pkt[2]));
__m256i desc0_1 =
_mm256_set_epi64x
(hi_qw1,
- pkt[1]->buf_iova + pkt[1]->data_off,
+ _PKT_DATA_OFF_U64(pkt[1]),
hi_qw0,
- pkt[0]->buf_iova + pkt[0]->data_off);
+ _PKT_DATA_OFF_U64(pkt[0]));
_mm256_store_si256((void *)(txdp + 2), desc2_3);
_mm256_store_si256((void *)txdp, desc0_1);
}
diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c
index 5bfd5152df..3c74331a5d 100644
--- a/drivers/net/ice/ice_rxtx_vec_avx512.c
+++ b/drivers/net/ice/ice_rxtx_vec_avx512.c
@@ -56,8 +56,14 @@ ice_rxq_rearm(struct ice_rx_queue *rxq)
}
}
+#if RTE_IOVA_AS_PA
const __m512i iova_offsets = _mm512_set1_epi64
(offsetof(struct rte_mbuf, buf_iova));
+#else
+ const __m512i iova_offsets = _mm512_set1_epi64
+ (offsetof(struct rte_mbuf, buf_addr));
+#endif
+
const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
@@ -1092,8 +1098,7 @@ ice_vtx1(volatile struct ice_tx_desc *txdp,
if (do_offload)
ice_txd_enable_offload(pkt, &high_qw);
- __m128i descriptor = _mm_set_epi64x(high_qw,
- pkt->buf_iova + pkt->data_off);
+ __m128i descriptor = _mm_set_epi64x(high_qw, _PKT_DATA_OFF_U64(pkt));
_mm_store_si128((__m128i *)txdp, descriptor);
}
@@ -1133,13 +1138,13 @@ ice_vtx(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkt,
__m512i desc0_3 =
_mm512_set_epi64
(hi_qw3,
- pkt[3]->buf_iova + pkt[3]->data_off,
+ _PKT_DATA_OFF_U64(pkt[3]),
hi_qw2,
- pkt[2]->buf_iova + pkt[2]->data_off,
+ _PKT_DATA_OFF_U64(pkt[2]),
hi_qw1,
- pkt[1]->buf_iova + pkt[1]->data_off,
+ _PKT_DATA_OFF_U64(pkt[1]),
hi_qw0,
- pkt[0]->buf_iova + pkt[0]->data_off);
+ _PKT_DATA_OFF_U64(pkt[0]));
_mm512_storeu_si512((void *)txdp, desc0_3);
}
--
2.31.1
next prev parent reply other threads:[~2022-12-11 13:41 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-11 21:52 [PATCH 0/3] support no IOVA as PA mode for some Intel NIC Qi Zhang
2022-12-11 21:52 ` Qi Zhang [this message]
2022-12-11 21:52 ` [PATCH 2/3] net/i40e: support no IOVA as PA mode Qi Zhang
2022-12-11 21:52 ` [PATCH 3/3] net/iavf: " Qi Zhang
2022-12-12 0:47 ` [PATCH 0/3] support no IOVA as PA mode for some Intel NIC Zhang, Qi Z
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