From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BEFE4A0545; Tue, 20 Dec 2022 20:29:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A9BCC42D86; Tue, 20 Dec 2022 20:27:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0E48C42D1D for ; Tue, 20 Dec 2022 20:26:59 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BKD9Qse004952 for ; Tue, 20 Dec 2022 11:26:59 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=Oktjw+qQKwwigFftLJE+/YmP3d3HRH1Tkb2k7yXw7cM=; b=B8GAjYp2lD538+Y4v1BdLUVP2w/L7mC+gIS2T1sEi7T4dwIwB+qJ6mwmOX5eq/v6R8ZW z5y2vBud+rI5poqu0zw4MOobwRMDP8j6umrO6DPMocsqA5BUhaAwED3KUjjNkozdR+/1 dh3hOmQBCCAG7y/WchdHydX/EM/FctSaRLXhnKBOGrBGgYsFNyLr9sEAfTVJxwjgoTx5 ihsBPhf7OVSbQyYQ/VBITUr/EQ08W1h5mMKl5Sfe63suUKOAZtxRvNAk5mTk7a+WuoPC 2R+YYpV1F3MV/7CQ2SR55nj8R9jeB7Wf7GaCo8WJj6vOttmRthc6iO6n6QtBKuNAybrj zA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mkapj2tpx-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Dec 2022 11:26:59 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 11:26:57 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 20 Dec 2022 11:26:57 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 509923F706F; Tue, 20 Dec 2022 11:26:57 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v3 22/38] ml/cnxk: add support to get IO buffer sizes Date: Tue, 20 Dec 2022 11:26:29 -0800 Message-ID: <20221220192645.14042-23-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220192645.14042-1-syalavarthi@marvell.com> References: <20221208201806.21893-1-syalavarthi@marvell.com> <20221220192645.14042-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: qzoDYdm6PuqosMf86Dz_GTsx35cbyUAp X-Proofpoint-GUID: qzoDYdm6PuqosMf86Dz_GTsx35cbyUAp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-20_06,2022-12-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added driver functions to get input and output buffer sizes for a given batch size. This function would compute the buffer size based on specific requirements of the device. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 55be5d2d29..d825c72a8e 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -935,6 +935,54 @@ cn10k_ml_model_params_update(struct rte_ml_dev *dev, int16_t model_id, void *buf return 0; } +static int +cn10k_ml_io_input_size_get(struct rte_ml_dev *dev, int16_t model_id, uint32_t nb_batches, + uint64_t *input_qsize, uint64_t *input_dsize) +{ + struct cn10k_ml_model *model; + + model = dev->data->models[model_id]; + + if (model == NULL) { + plt_err("Invalid model_id = %d", model_id); + return -EINVAL; + } + + if (input_qsize != NULL) + *input_qsize = PLT_U64_CAST(model->addr.total_input_sz_q * + PLT_DIV_CEIL(nb_batches, model->batch_size)); + + if (input_dsize != NULL) + *input_dsize = PLT_U64_CAST(model->addr.total_input_sz_d * + PLT_DIV_CEIL(nb_batches, model->batch_size)); + + return 0; +} + +static int +cn10k_ml_io_output_size_get(struct rte_ml_dev *dev, int16_t model_id, uint32_t nb_batches, + uint64_t *output_qsize, uint64_t *output_dsize) +{ + struct cn10k_ml_model *model; + + model = dev->data->models[model_id]; + + if (model == NULL) { + plt_err("Invalid model_id = %d", model_id); + return -EINVAL; + } + + if (output_qsize != NULL) + *output_qsize = PLT_U64_CAST(model->addr.total_output_sz_q * + PLT_DIV_CEIL(nb_batches, model->batch_size)); + + if (output_dsize != NULL) + *output_dsize = PLT_U64_CAST(model->addr.total_output_sz_d * + PLT_DIV_CEIL(nb_batches, model->batch_size)); + + return 0; +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ .dev_info_get = cn10k_ml_dev_info_get, @@ -954,4 +1002,8 @@ struct rte_ml_dev_ops cn10k_ml_ops = { .model_stop = cn10k_ml_model_stop, .model_info_get = cn10k_ml_model_info_get, .model_params_update = cn10k_ml_model_params_update, + + /* I/O ops */ + .io_input_size_get = cn10k_ml_io_input_size_get, + .io_output_size_get = cn10k_ml_io_output_size_get, }; -- 2.17.1